PCF8564AU/5GB/1(2010) 查看數據表（PDF） - NXP Semiconductors.
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PCF8564AU/5GB/1 Datasheet PDF : 45 Pages
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NXP Semiconductors
PCF8564A
Real time clock and calendar
8.3 Control registers
8.3.1 Register Control_1
Table 5. Control_1 - control and status register 1 (address 00h) bit description
Bit
Symbol Value
Description
7
TEST1
0[1]
normal mode;
• must be set to logic 0 during normal operations
1
EXT_CLK test mode (see Section 8.9)
6
N
0[2]
default value
5
STOP
0[1]
1
RTC source clock runs
• RTC divider chain flip-flops are asynchronously set to logic 0
• the RTC clock is stopped (CLKOUT at 32.768 kHz is still available)
4
N
0[2]
default value
3
TESTC 0
Power-On Reset (POR) override facility is disabled;
• set to logic 0 for normal operation (see Section 8.11.1)
1[1]
Power-On Reset (POR) override is enabled
2 to 0 N
000[2]
default value
Reference
Section 8.9
Section 8.10
Section 8.11.1
[1] Default value.
[2] Bits labeled as N should always be written with logic 0.
8.3.2 Register Control_2
Table 6. Control_2 - control and status register 2 (address 01h) bit description
Bit
Symbol Value
Description
7 to 5 N
000[1]
default value
4
TI_TP
0[2]
INT is active when TF is active (subject to the status of TIE)
1
INT pulses active according to Table 7 (subject to the status of TIE);
• Remark: note that if AF and AIE are active then INT will be
permanently active
3
AF
0[2]
alarm flag inactive
1
alarm flag active
2
TF
0[2]
timer flag inactive
1
timer flag active
1
AIE
0[2]
alarm interrupt disabled
1
alarm interrupt enabled
0
TIE
0[2]
timer interrupt disabled
1
timer interrupt enabled
Reference
Section 8.3.2.1
and
Section 8.8
Section 8.3.2.1
Section 8.3.2.1
Section 8.3.2.1
Section 8.3.2.1
[1] Bits labeled as N should always be written with logic 0.
[2] Default value.
PCF8564A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 02 — 30 September 2010
© NXP B.V. 2010. All rights reserved.
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