PCF8564AU/5BB/1 查看數據表（PDF） - NXP Semiconductors.

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PCF8564AU/5BB/1

Real time clock and calendar

NXP Semiconductors. 

NXP Semiconductors

PCF8564A

Real time clock and calendar

8.3.2.1 Interrupt output

Bits TF and AF: When an alarm occurs, AF is set to 1. Similarly, at the end of a timer

countdown, TF is set to 1. These bits maintain their value until overwritten by command. If

both timer and alarm interrupts are required in the application, the source of the interrupt

can be determined by reading these bits. To prevent one flag being overwritten while

clearing another, a logic AND is performed during a write access.

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When bits TIE and AIE are disabled, pin INT will remain high-impedance.

Fig 3. Interrupt scheme

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Bits TIE and AIE: These bits activate or deactivate the generation of an interrupt when

TF or AF is asserted respectively. The interrupt is the logical OR of these two conditions

when both AIE and TIE are set.

Countdown timer interrupts: The pulse generator for the countdown timer interrupt uses

an internal clock and is dependent on the selected source clock for the countdown timer

and on the countdown value TV. As a consequence, the width of the interrupt pulse varies

(see Table 8).

Table 8. INT operation (bit TI_TP = 1)[1]

Source clock (Hz)

INT period (s)

TV = 1[2]

4 096

64

1

1⁄60

1⁄8 192

1⁄128

1⁄64

1⁄64

[1] TF and INT become active simultaneously.

[2] TV = loaded countdown value. Timer is stopped when TV = 0.

TV > 1

1⁄4 096

1⁄64

1⁄64

1⁄64

PCF8564A

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 3 — 26 August 2013

© NXP B.V. 2013. All rights reserved.

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