PCF8578 查看數據表（PDF） - NXP Semiconductors.

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PCF8578

LCD row/column driver for dot matrix graphic displays

NXP Semiconductors. 

NXP Semiconductors

PCF8578

LCD row/column driver for dot matrix graphic displays

Table 5 shows the relative values of the resistors required in the configuration of Figure 5

to produce the standard multiplex rates.

Table 5. Multiplex rates and resistor values for Figure 5

Resistors

Multiplex rate (1:n)

n=8

R1

R

R2

( n – 2)R

R3

(3 – n)R

n = 16, 24, 32

R

R

( n – 3)R

8.2 Power-on reset

At power-on the PCF8578 resets to a defined starting condition as follows:

1. Display blank

2. 1:32 multiplex rate, row mode

3. Start bank 0 selected

4. Data pointer is set to X, Y address 0, 0

5. Character mode

6. Subaddress counter is set to 0

7. I2C-bus interface is initialized

Remark: Do not transfer data on the I2C-bus for at least 1 ms after power-on to allow the

reset action to complete.

8.3 Multiplexed LCD bias generation

The bias levels required to produce maximum contrast depend on the multiplex rate and

the LCD threshold voltage (Vth). Vth is typically defined as the RMS voltage at which the

LCD exhibits 10 % contrast. Table 6 shows the optimum voltage bias levels and Table 7

the discrimination ratios (D) for the different multiplex rates as functions of Voper.

Voper = VDD – VLCD

(1)

The RMS on-state voltage (Von(RMS)) for the LCD is calculated with the equation

V on(RMS)

=

Voper

1n--

+

---------n-----–----1------

n( n + 1)

(2)

and the RMS off-state voltage (Voff(RMS)) with the equation

V off (RMS) = Voper ----2-n--(-(------n-n----–+----1-1---)-)--2

(3)

PCF8578_6

Product data sheet

Rev. 06 — 5 May 2009

© NXP B.V. 2009. All rights reserved.

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