PCF8578 查看數據表（PDF） - NXP Semiconductors.
零件编号
产品描述 (功能)
生产厂家
PCF8578 Datasheet PDF : 46 Pages
| |||
NXP Semiconductors
PCF8578
LCD row/column driver for dot matrix graphic displays
8. Functional description
8.1 Display configurations
The PCF8578 row and column driver is designed for use in one of three ways:
• Stand-alone row and column driver for small displays (mixed mode)
• Row and column driver with cascaded PCF8579s (mixed mode)
• Row driver with cascaded PCF8579s (mixed mode and row mode)
Table 4. Possible display configurations
Applicatio Multiplex rate Mixed mode
Row mode
Typical applications
n
Rows Columns Rows Columns
stand alone 1:8
1:16
8
32
-
-
16
24
-
-
small digital or
alphanumeric displays
1:24
24
16
-
-
1:32
32
8
-
-
with
1:8
PCF8579 1:16
1:24
8[1]
16[1]
24[1]
632[1]
624[1]
616[1]
8 × 4[2] 640[2]
16 × 2[2] 640[2]
24[2]
640[2]
alphanumeric displays
and dot matrix graphic
displays
1:32
32[1]
608[1]
32[2]
640[2]
[1] Using 15 PCF8579s.
[2] Using 16 PCF8579s.
In mixed mode, the device functions as both a row and column driver. It can be used in
small stand-alone applications, or for larger displays with up to 15 PCF8579s
(31 PCF8579s when two slave addresses are used). See Table 4 for common display
configurations.
In row mode, the device functions as a row driver with up to 32 row outputs and provides
the clock and synchronization signals for the PCF8579. Up to 16 PCF8579s can normally
be cascaded (32 when two slave addresses are used).
Timing signals are derived from the on-chip oscillator, whose frequency is determined by
the value of the resistor connected between pin OSC and pin VSS.
Five commands are available to configure and control the operation of the device.
Communication is made via a two-line bidirectional I2C-bus. The device may have one of
two slave addresses. The only difference between these slave addresses is the least
significant bit, which is set by the logic level applied to SA0. The PCF8578 and PCF8579
have different subaddresses. The subaddress of the PCF8578 is only defined in mixed
mode and is fixed at 0111 100 (see Section 8.8.7 on page 19). The RAM may only be
accessed in mixed mode and data is loaded as described for the PCF8579.
Bias levels may be generated by an external potential divider with appropriate decoupling
capacitors. For large displays, bias sources with high drive capability should be used. A
typical mixed mode system operating with up to 15 PCF8579s is shown in Figure 5 (a
stand-alone system would be identical but without the PCF8579).
PCF8578_6
Product data sheet
Rev. 06 — 5 May 2009
© NXP B.V. 2009. All rights reserved.
8 of 46
Share Link: 