PCK2000M 查看數據表（PDF） - Philips Electronics
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PCK2000M Datasheet PDF : 12 Pages
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Philips Semiconductors
CK97 (66/100MHz) Mobile System Clock Generator
Product specification
PCK2000M
ALL CLOCK OUTPUTS
SYMBOL
PARAMETER
TEST CONDITIONS
NOTES
LIMITS
Tamb = 0°C to +70°C
MIN
MAX
UNIT
TPZL, TPZH
TPLZ, TPHZ
Output enable time
Output disable time
1.0
8.0
ns
1.0
8.0
ns
NOTES:
1. See Figure 3 for measure points.
2. Period, jitter, offset, and skew are measured on the rising edge @ 1.25V for 2.5V clocks and @ 1.5V for 3.3V clocks.
3. The PCICLK is the CPUCLK divided by two at CPUCLK = 66.6MHz. PCICLK is the CPUCLK divided by three at CPUCLK = 100MHz.
4. The CPUCLK must always lead the PCICLK as shown in Figure 2.
5. THKH is measured @ 2.0V as shown in Figure 4.
6. THKL is measured @ 0.4V as shown in Figure 4.
7. The time is specified from when VDDQ achieves its nominal operating level (typical condition is VDDQ = 3.3V) until the frequency output is
stable and operating within specification.
8. Defined as once the clock is at its nominal operating frequency, the adjacent period changes cannot exceed the time specified.
9. THRISE and THFALL are measured as a transition through the threshold region VOL = 0.4V and VOH = 2.0V (1mA) JEDEC specification.
10. THRISE and THFALL (REF, PCI) are measured as a transition through the threshold region VOL = 0.4V and VOH = 2.4V
AC WAVEFORMS
VM = 1.25V @ VDDQ2 and 1.5V @ VDDQ3
VX = VOL + 0.3V
VY = VOH –0.3V
VOL and VOH are the typical output voltage drop that occur with the
output load.
CPUCLK
1.25V
VDDQ2
VSS
CPUCLK
1.25V
VDDQ2
VSS
THSKW
SW00240
Figure 1. CPUCLK to CPUCLK skew
CPUCLK
1.25V
VDDQ2
VSS
PCICLK
1.5V
VDDQ3
VSS
THPOFFSET
SW00241
Figure 2. CPUCLK to PCICLK offset
2.0
2.5V CLOCKING 1.25
INTERFACE
0.4
THKP
DUTY CYCLE
THKH
TRISE
TFALL
THKL
2.4
3.3V CLOCKING
INTERFACE
1.5
(TTL)
0.4
TPKH
TPKP
TRISE
TFALL
TPKL
SW00242
Figure 3. 2.5V/3.3V Clock waveforms
1998 Sep 29
8
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