4255 查看數據表（PDF） - Allegro MicroSystems

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4255

8-Bit microcontroller

Allegro MicroSystems 

4255

8-BIT

MICROCONTROLLER

FUNCTIONAL DESCRIPTION (cont’d)

3 125 full steps per second (50 kHz/16). These frequen-

cies represent the attainable limits with the A4255.

Although not a necessity, a stepping clock with a 50%

duty cycle represents the simplest technique for providing

an appropriate (≤50 kHz) stepping clock rate. The step

clock varies depending upon the start, acceleration,

slewing, deceleration, and stop trajectories mandated by

the motion system control and ‘point-to-point’ timing

objectives.

Reset input

The preprogrammed microcontroller incorporates two

‘software’ reset states that are serially loaded with MS2,

MS1, and MS0 all high. However, the direct hardware

reset is actuated with a logic 0 (active low) on this input

An input low level defaults to the 0000 binary state and

sets the rotor to its natural (or detent) position with one-

phase energized.

Monitor output

An output low signal indicates a rotor alignment

corresponding to a single phase on position. Any changes

in the operating mode (microstepping to full-step, etc.)

should coincide with the interval that the monitor output is

in the low state. This alleviates noise problems, excessive

ringing, etc. that may result from changing the stepping

modes on-the-fly. Nonlinear (such as S-curve) accelera-

tion profiles can exploit this signal to achieve very

smooth, quiet stepper operation.

Shift clock output

This I/O terminal serves a dual purpose. On power

up, the microcontroller samples this terminal as an input.

Connecting a pull-up resistor results in 1/8th-step format;

while a pull-down resistor configures the controller for its

1/16th-step mode (A3957 only). This provides versatility,

simplicity, and cost-effectiveness for most users.

Operating in its output mode, this I/O constitutes the

shift clock signal for the 74HC595. Data is transferred

from the microcontroller serial-data output to the serial-

data input of the 74HC595. This 8-bit serial format is

converted into parallel signals controlling the 3-bit (or 4-

bit) DAC input lines to the two microstepping power ICs.

Serial data from the serial data output is valid on the low-

to-high clock transitions and eight clock pulses shift serial

control signals into the 74HC595. A basic timing diagram

(showing serial data, shift clock, and strobe) is depicted.

Signal timing is controlled by the preprogrammed micro-

controller; data entered into the 74HC595 shift register is

then latched by the low-to-high transition of the strobe

input.

SDO

D7

D6

D5

D4

D3

D2

D1

D0

SCLK

ST

Dwg. WP-040A

Serial data, shift clock, and strobe

Serial data output

The binary signal instructions that control each of the

microstepping power ICs is shown in table 1. The first

3-bits (or 4-bits) control the digital-to-analog conversion

in one power IC, while the next 3 (or 4-bits) ratio the

second power driver current. The microcontroller moni-

tors all the various static inputs (i.e., Direction, Mode

Selects, Reset), and by exploiting the Stepping Clock for

its input frequency, transfers the 8-bit data commands to

the power driver ICs via the serial-to-parallel interface IC.

The microcontroller utilizes look-up tables to provide

overall control of direction, stepping format, and recircu-

lation mode (PFD). The microcontroller reads inputs and

then outputs time-based signals to control both microstep-

ping ICs.

Strobe output

After the 8-bit serial data has been loaded into the

shift register, a low-to-high transition on the strobe output

transfers the serial data from the shift register into the

eight ‘D’ flip-flops that compose the parallel-data outputs.

This ‘latched’ data controls microstepping current ratios

for both power ICs, and is ‘updated’ after eight step

clocks.

www.allegromicro.com

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