42551-00 查看數據表（PDF） - Peregrine Semiconductor Corp.
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42551-00 Datasheet PDF : 9 Pages
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PE42551
Product Specification
Evaluation Kit
The SPDT Switch Evaluation Kit board was
designed to ease customer evaluation of the
PE42551 SPDT switch. The RF common port is
connected through a 50 Ω transmission line to J2.
Port 1 and Port 2 are connected through 50 Ω
transmission lines to J1 and J3. A through
transmission line connects SMA connectors J4
and J5. This transmission line can be used to
estimate the loss of the PCB over the
environmental conditions being evaluated.
The board is constructed of a two metal layer
FR4 material with a total thickness of 0.032”. The
transmission lines were designed using a
coplanar waveguide with ground plane (28 mil
core, 47.6 mil width, 30 mil gap).
Good RF layout and prudent use of vias is critical
for obtaining the specified isolation performance
for the device shown in this datasheet.
J6 provides a means for controlling DC and
digital inputs to the device. The provided jumpers
short the package pin to ground for logic low.
When the jumper is removed, the pin is pulled up
to VDD for logic high. When the jumper is in place,
3 µA of current will flow through the 1MΩ pull up
resistor. This extra current should not be
attributed to the requirements of the device.
Figure 5. Evaluation Board Layouts
Peregrine Specification 101-0151
Figure 6. Evaluation Board Schematic
Peregrine Specification 102-0198
J6
HEADER 7X2
11
33
55
77
99
11 11
13 13
22
44
66
88
10 10
12 12
14 14
C1
R1
R2
DNI
1M
1M
J1
SMASM
1
50 OHM T-Line
1 GND
2 GND
3 RF1
4 GND
5 GND
U1
PE42551
GND 15
GND 14
RF2 13
GND 12
GND 11
C2
C3
DNI
DNI
50 OHM T-Line
J3
SMASM
1
J2
SMASM
1
50 OHM T-Line
Document No. 70-0350-02 │ www.psemi.com
J4
SMASM
1
50 OHM T-Line
J5
SMASM
1
©2010-2012 Peregrine Semiconductor Corp. All rights reserved.
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