PEB20525 查看數據表（PDF） - Infineon Technologies

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PEB20525

2 Channel Serial Optimized Communication Controller for HDLC/PPP

Infineon Technologies 

PEB 20525

Revision History:

Previous Version:

Page

(previous

Version)

Page

(current

Version)

33-35

36-38

81

84

n.a.

232, 235

n.a.

232

222

226

2000-09-14

DS 1

PASSAT V1.1 Preliminary Data Sheet, 09.99, DS2

Subjects (major changes since last revision)

Correction: signal ’OSR’ is multiplexed with signal ’CD’, signal

’OST’ is multiplexed with ’CTS’ (was vice versa)

corrected HDLC receive address recognition table

Added timing diagram for external DMA support signals

Added address timing diagram for Intel multiplexed mode

(signal ALE)

Chapter "Electrical Characteristics" updated with final

characterization results.

For questions on technology, delivery and prices please contact the Infineon

Technologies Offices in Germany or the Infineon Technologies Companies and

Representatives worldwide: see our webpage at http://www.infineon.com

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