PEB20525 查看數據表（PDF） - Infineon Technologies
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PEB20525 Datasheet PDF : 252 Pages
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PEB 20525
PEF 20525
List of Figures
Page
Figure 43
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Figure 80
HDLC Receive Data Processing in Address Mode 1 . . . . . . . . . . . . . . 87
HDLC Receive Data Processing in Address Mode 0 . . . . . . . . . . . . . . 87
SCC Transmit Data Flow (HDLC Modes) . . . . . . . . . . . . . . . . . . . . . . 89
PPP Mapping/Unmapping Example. . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Processing of Received Frames in Auto Mode . . . . . . . . . . . . . . . . . . 97
Timer Procedure/Poll Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Transmission/Reception of I-Frames and Flow Control . . . . . . . . . . . 100
Flow Control: Reception of S-Commands and Protocol Errors . . . . . 100
No Data to Send: Data Reception/Transmission . . . . . . . . . . . . . . . . 103
Data Transmission (without error), Data Transmission (with error) . . 103
Interrupt Driven Data Transmission (Flow Diagram) . . . . . . . . . . . . . 216
Interrupt Driven Data Reception (Flow Diagram) . . . . . . . . . . . . . . . . 218
DMA Transmit (Single Buffer per Packet) . . . . . . . . . . . . . . . . . . . . . 220
Fragmented DMA Transmission (Multiple Buffers per Packet) . . . . . 221
DMA Receive (Single Buffer per Packet) . . . . . . . . . . . . . . . . . . . . . . 223
Fragmented Reception per DMA (Example) . . . . . . . . . . . . . . . . . . . 224
Fragmented Reception Sequence (Example) . . . . . . . . . . . . . . . . . . 225
Input/Output Waveform for AC Tests . . . . . . . . . . . . . . . . . . . . . . . . . 228
Microprocessor Interface Clock Timing . . . . . . . . . . . . . . . . . . . . . . . 230
Infineon/Intel Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Infineon/Intel Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Infineon/Intel DMA Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . 232
Infineon/Intel DMA Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . 232
Infineon/Intel Multiplexed Address Timing . . . . . . . . . . . . . . . . . . . . . 232
Motorola Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Motorola Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Motorola DMA Read Cycle Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Motorola DMA Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Receive Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Transmit Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Clock Mode 1 Strobe Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Clock Mode 4 Receive Gating Timing . . . . . . . . . . . . . . . . . . . . . . . . 242
Clock Mode 4 Transmit Gating Timing. . . . . . . . . . . . . . . . . . . . . . . . 242
Clock Mode 5 Frame Synchronisation Timing . . . . . . . . . . . . . . . . . . 243
Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
JTAG-Boundary Scan Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Block Diagram of Test Access Port and Boundary Scan Unit . . . . . . 246
Data Sheet
9
2000-09-14
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