29F52 查看數據表（PDF） - Fairchild Semiconductor
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29F52 Datasheet PDF : 8 Pages
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Connection Diagrams
Pin Assignment for DIP and SOIC
29F52
Pin Assignment for DIP
29F53
Unit Loading/Fan Out
Pin Names
Description
A0–A7
B0–B7
OEA
CPA
CEA
OEB
CPB
CEB
A-Register Inputs/
B-Register 3-STATE Outputs
B Register Inputs/
A-Register 3-STATE Outputs
Output Enable A-Register
A-Register Clock
A-Register Clock Enable
Output Enable B-Register
B-Register Clock
B-Register Clock Enable
U.L.
HIGH/LOW
3.5/1.083
150/40 (33.3)
3.5/1.083
600/106.6 (80)
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
Input IIH/IIL
Output IOH/IOL
70 µA/0.65 mA
−3 mA/24 mA (20 mA)
70 µA/0.65 mA
−12 mA/64 mA (48 mA)
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
Output Control
Internal Y-Output
OE
Q 29F52 29F53
Function
H
X
Z
Z Disable Outputs
L
L
L
H
Enable Outputs
L
H
H
L
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = HIGH Impedance
N = LOW-to-HIGH Transition
NC = No Change
Register Function Table
(Applies to A or B Register)
Inputs
Internal
D CP CE
Q
Function
X
X
H
NC Hold Data
L
N
L
H
N
L
L
Load Data
H
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