HT48CA3(2003) 查看數據表（PDF） - Holtek Semiconductor

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HT48CA3
(Rev.:2003)

8-Bit Remote Type MCU

Holtek Semiconductor 

HT48CA3

in port A can be independently selected to wake up the

device by mask option. Awakening from an I/O port

stimulus, the program will resume execution of the next

instruction. If it awakens from an interrupt, two se-

quence may occur. If the related interrupt is disabled or

the interrupt is enabled but the stack is full, the program

will resume execution at the next instruction. If the inter-

rupt is enabled and the stack is not full, the regular inter-

rupt response takes place. If an interrupt request flag is

set to ²1² before entering the HALT mode, the wake-up

function of the related interrupt will be disabled. Once a

wake-up event occurs, it takes 1024 tSYS (system clock

period) to resume normal operation. In other words, a

dummy period will be inserted after a wake-up. If the

wake-up results from an interrupt acknowledge signal,

the actual interrupt subroutine execution will be delayed

by one or more cycles. If the wake-up results in the next

instruction execution, this will be executed immediately

after the dummy period is finished.

To minimize power consumption, all the I/O pins should

be carefully managed before entering the HALT status.

Reset

There are three ways in which a reset can occur:

· RES reset during normal operation

· RES reset during HALT

· WDT time-out reset during normal operation

The WDT time-out during HALT is different from other

chip reset conditions, since it can perform a ²warm re -

set² that resets only the PC and SP, leaving the other cir-

cuits in their original state. Some registers remain un-

changed during other reset conditions. Most registers

are reset to the ²initial condition² when the reset condi-

tions are met. By examining the PD and TO flags, the

program can distinguish between different ²chip resets².

TO PD

RESET Conditions

0 0 RES reset during power-up

u u RES reset during normal operation

0 1 RES wake-up HALT

1 u WDT time-out during normal operation

1 1 WDT wake-up HALT

Note: ²u² stands for unchanged

To guarantee that the system oscillator is started and

stabilized, the SST (System Start-up Timer) provides an

extra-delay of 1024 system clock pulses when the sys-

tem reset (power-up, WDT time-out or RES reset) or the

system awakes from the HALT state.

When a system reset occurs, the SST delay is added

during the reset period. Any wake-up from HALT will en-

able the SST delay.

The functional unit chip reset status are shown below.

PC

000H

Interrupt

Disable

Prescaler

Clear

WDT

Clear. After master reset,

WDT begins counting

Timer/Event Counter Off

Input/output Ports

Input mode

SP

Points to the top of the stack

VDD

RES

S S T T im e - o u t

C h ip R e s e t

tS S T

Reset timing chart

V DD

RES

Reset circuit

H A LT

W DT

RES

O SC1

SST

1 0 - b it R ip p le

C o u n te r

S y s te m R e s e t

W a rm R e s e t

C o ld

R eset

Reset configuration

Rev. 1.40

10

July 16, 2003

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