DM74LS259N 查看數據表（PDF） - Fairchild Semiconductor
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DM74LS259N Datasheet PDF : 6 Pages
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Connection Diagram
Function Table
Inputs
Clear E
HL
HH
LL
LH
Output of
Addressed
Latch
D
Qi0
D
L
Each
Other
Function
Output
Qi0 Addressable Latch
Qi0 Memory
L 8-Line Demultiplexer
L Clear
Latch Selection Table
Select Inputs
Latch
C
B
A
Addressed
L
L
L
0
L
L
H
1
L
H
L
2
L
H
H
3
H
L
L
4
H
L
H
5
H
H
L
6
H
H
H
7
H = HIGH Level
L = LOW Level
D = the Level of the Data Input
Qi0 = the Level of Qi (i = 0, 1,…7, as Appropriate) before the Indicated
Steady-State Input Conditions Were Established.
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