SN54LS323 查看數據表（PDF） - Motorola => Freescale
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SN54LS323 Datasheet PDF : 5 Pages
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S1 19 S0 1
SN54 / 74LS323
LOGIC DIAGRAM
DS0 11
9
SR
12
CP
Q0 8
2
OE1
OE2 3
18
DS7
D CP
Q
D CP
Q
D CP
Q
D CP
Q
D CP
Q
D CP
Q
D CP
Q
D CP
17
Q
Q7
7
13
6
I/O0
I/O1
I/O2
14
5
I/O3
I/O4
15
4
I/O5
I/O6
16
I/O7
FUNCTIONAL DESCRIPTION
The logic diagram and truth table indicate the functional
characteristics of the SN54/74LS323 Universal Shift/Storage
Register. This device is similar in operation to the
SN54/74LS299 except for synchronous reset. A partial list of
the common features are described below:
1. They use eight D-type edge-triggered flip-flops that re-
spond only to the LOW-to-HIGH transition of the Clock
(CP). The only timing restriction, therefore, is that the mode
control (S0, S1) and data inputs (DS0, DS7, I/O0–I/O7) may
be stable at least a setup time prior to the positive transition
of the Clock Pulse.
2. When S0 = S1 = 1, I/O0–I/O7 are parallel inputs to flip-flops
Q0–Q7 respectively, and the outputs of Q0–Q7 are in the
high impedance state regardless of the state of OE1 or
OE2.
An important unique feature of the SN54/74LS323 is a fully
Synchronous Reset that requires only to be stable at least one
setup time prior to the positive transition of the Clock Pulse.
TRUTH TABLE
INPUTS
RESPONSE
SR S1 S0 OE1 OE2 CP DS0 DS7
LXXH X
LXX X H
LHH X X
X
X
X
X
Synchronous Reset; Q0 = Q7 = LOW
I/O voltage undetermined
XX
LLX L L
LXL L L
X X Synchronous Reset; Q0 = Q7 = LOW
X X I/O voltage LOW
HLHX X
HLH L L
D X Shift Right; D Q0; Q0 Q1; etc.
D X Shift Right; D Q0 & I/O0; Q0 Q1 & I/O1; etc.
HHL X X
HHL L L
X D Shift Left; D Q7; Q7 Q6; etc.
X D Shift Left; D Q7 & I/O7; Q7 Q6 & I/O6; etc.
HHH X X
X X Parallel Load I/On Qn
HL
L
H
X
X
X
X Hold; I/O Voltage Undetermined
HLL X HXX X
HL L
L
LXX
X Hold; I/On = Qn
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
FAST AND LS TTL DATA
5-2
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