PIC16LC72AT-20IJW 查看數據表（PDF） - Microchip Technology

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PIC16LC72AT-20IJW

28-Pin 8-Bit CMOS Microcontrollers

Microchip Technology 

PIC16C62B/72A

2.2.2 SPECIAL FUNCTION REGISTERS

The Special Function Registers are registers used by

the CPU and Peripheral Modules for controlling the

desired operation of the device. These registers are

implemented as static RAM. A list of these registers is

given in Table 2-1.

The Special Function Registers can be classified into

two sets; core (CPU) and peripheral. Those registers

associated with the core functions are described in

detail in this section. Those related to the operation of

the peripheral features are described in detail in the

peripheral feature section.

TABLE 2-1 SPECIAL FUNCTION REGISTER SUMMARY

Addr

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on: Value on all

POR, other resets

BOR

(4)

Bank 0

00h

INDF(1)

Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000

01h

TMR0

Timer0 module’s register

02h

PCL(1)

Program Counter's (PC) Least Significant Byte

03h

STATUS(1)

IRP(5)

RP1(5)

RP0

TO

PD

Z

DC

04h

FSR(1)

Indirect data memory address pointer

05h

PORTA(6,7)

—

— PORTA Data Latch when written: PORTA pins when read

06h

PORTB(6,7) PORTB Data Latch when written: PORTB pins when read

07h

PORTC(6,7) PORTC Data Latch when written: PORTC pins when read

xxxx xxxx uuuu uuuu

0000 0000 0000 0000

C

0001 1xxx 000q quuu

xxxx xxxx uuuu uuuu

--0x 0000 --0u 0000

xxxx xxxx uuuu uuuu

xxxx xxxx uuuu uuuu

08h-09h

0Ah

0Bh

0Ch

—

PCLATH(1,2)

INTCON(1)

PIR1

Unimplemented

—

—

GIE

PEIE

—

ADIF(3)

—

T0IE

—

—

—

Write Buffer for the upper 5 bits of the Program Counter

---0 0000 ---0 0000

INTE

RBIE

T0IF

INTF

RBIF 0000 000x 0000 000u

—

SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000

0Dh

—

Unimplemented

—

—

0Eh

TMR1L

Holding register for the Least Significant Byte of the 16-bit TMR1 register

xxxx xxxx uuuu uuuu

0Fh

TMR1H

Holding register for the Most Significant Byte of the 16-bit TMR1 register

xxxx xxxx uuuu uuuu

10h

T1CON

—

— T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu

11h

TMR2

Timer2 module’s register

0000 0000 0000 0000

12h

T2CON

— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000

13h

SSPBUF

Synchronous Serial Port Receive Buffer/Transmit Register

xxxx xxxx uuuu uuuu

14h

SSPCON

WCOL SSPOV SSPEN CKP

SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000

15h

CCPR1L

Capture/Compare/PWM Register1 (LSB)

xxxx xxxx uuuu uuuu

16h

CCPR1H

Capture/Compare/PWM Register1 (MSB)

xxxx xxxx uuuu uuuu

17h

CCP1CON

—

—

CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000

18h-1Dh

—

Unimplemented

—

—

1Eh

ADRES(3)

A/D Result Register

xxxx xxxx uuuu uuuu

1Fh

ADCON0(3)

ADCS1 ADCS0 CHS2

CHS1

CHS0 GO/DONE —

ADON 0000 00-0 0000 00-0

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ’0’,

Shaded locations are unimplemented, read as ’0’.

Note 1: These registers can be addressed from either bank.

2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<12:8> whose contents

are transferred to the upper byte of the program counter.

3: A/D not implemented on the PIC16C62B, maintain as ’0’.

4: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.

5: The IRP and RP1 bits are reserved. Always maintain these bits clear.

6: On any device reset, these pins are configured as inputs.

7: This is the value that will be in the port output latch.

© 1999 Microchip Technology Inc.

Preliminary

DS35008B-page 9

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