HI1396(1997) 查看數據表（PDF） - Intersil
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HI1396 Datasheet PDF : 10 Pages
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HI1396
Electrical Specifications TA = 25oC, AVEE = DVEE = -5.2V, VRT = 0V, VRB = -2V (Note 1) (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
TIMING CHARACTERISTICS
Output Rise Time, tr
Output Fall Time, tf
Output Delay, tOD
H Pulse Width of Clock, tPW1
L Pulse Width of Clock, tPW0
DYNAMIC CHARACTERISTICS
Maximum Conversion Rate, fC
Aperture Jitter, tAJ
Sampling Delay, tDS
Signal to Noise Ratio (SINAD)
= R-----M-----S------N--R--o--M-i--s--S-e----+-S----iD-g----ni--s-a--t-l--o---r---t--i--o----n-
Error Rate
Differential Gain Error, DG
Differential Phase Error, DP
RL = 50Ω to -2V, 20% to 80%
RL = 50Ω to -2V, 20% to 80%
Error Rate 10-9 TPS (Note 2)
Input = 1MHz, Full Scale
fC = 125 MSPS
Input = 31.5MHz, Full Scale
fC = 125 MSPS
Input = 31.249MHz, Full Scale
Error > 16 LSB, fC = 125 MSPS
NTSC 40 IRE Mod.
Ramp, fC = 125 MSPS
0.5
0.9
1.2
0.5
1.0
1.3
3.0
3.6
4.2
4.0
-
-
4.0
-
-
125
-
-
-
10
-
-
1.5
-
-
46
-
-
40
-
-
-
10-9
-
1.0
-
-
0.5
-
POWER SUPPLY CHARACTERISTICS
Supply Current, IEE
Power Consumption
Note 3
-230
-160
-
-
870
-
NOTES:
1. Electrical Specifications guaranteed within stated operating conditions.
2. TPS: Times Per Sample.
3. PD = IEE • VEE + -(--V----R----TR-----R–----E-V---F-R----B----)--2-
UNIT
ns
ns
ns
ns
ns
MSPS
ps
ns
dB
dB
TPS
(Note 2)
%
Degree
mA
mW
4. TA specified in still air and without heat sink. To extend temperature range, appropriate heat management techniques must be employed.
Timing Diagram
ANALOG IN
CLK
CLK
N
tPW1
tPW0
N+1
N+2
DIGITAL OUT
tOD
N-1
80%
20%
N
20%
N+1
80%
tr
tf
FIGURE 1.
4-1159
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