HI1396(1997) 查看數據表（PDF） - Intersil
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HI1396 Datasheet PDF : 10 Pages
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HI1396
Pin Descriptions and I/O Pin Equivalent Circuits
PIN NUMBER
DIP
LCC
STANDARD
VOLTAGE
SYMBOL I/O LEVEL
29, 31, 49, 51, AGND -
0V
33, 35 53, 55
EQUIVALENT CIRCUIT
1, 25, 41, 42, AVEE
-
26, 38, 62, 63,
39
67
21
35
CLK
I
20
34
CLK
-5.2V
ECL
DGND1
CLK
CLK
R
R
R
R
DESCRIPTION
Analog GND. Used as GND for
input buffers and latches of
comparators. Isolated from
DGND1, DGND2.
Analog VEE -5.2V (Typ). Internally
connected to DVEE (Resistance:
4Ω to 6Ω). Bypass with 0.1µF to
AGND.
CLK Input.
Input complementary to CLK.
When left open pulled down to
-1.3V. Device is operable without
CLK input, but use of
complementary inputs of CLK and
CLK is recommended to obtain
stable high speed operation.
DVEE
RR
5, 16 7, 24 DGND1 -
6, 15 8, 23 DGND2 -
4, 17 5, 30
DVEE
-
0V
0V
-5.2V
7
14
8
15
9
16
10
17
11
18
12
19
13
20
14
21
D0
O
ECL
D1
D2
D3
D4
D5
D6
D7
DGND2
DI
Digital GND for internal circuits.
Digital GND for output transistors.
Digital VEE. Internally connected
to AVEE (resistance: 4Ω to 6Ω).
Bypass with 0.1µF to DGND
LSB of data outputs. External
pull-down resistor is required.
Data outputs. External pull-down
resistors are required.
DVEE
MSB of data outputs. External
pull-down resistor is required.
4-1160
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