PLL102-03 查看數據表（PDF） - PhaseLink Corporation

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PLL102-03

Low Skew Output Buffer

PhaseLink Corporation 

3. Switching Characteristics

PARAMETERS

Output Frequency

Duty Cycle ( t2 ÷ t1 )

Duty Cycle ( t2 ÷ t1 )

Rise Time

Fall Time

Output to Output Skew

Delay, REF Rising Edge to

CLKOUT Rising Edge

Device to Device Skew

Cycle to Cycle Jitter

PLL Lock Time

Jitter; Absolute Jitter

Jitter; 1-sigma

SYMBOL

DESCRIPTION

t1

Dt1

Measured at 1.4V, CL=30pF

Dt2 Measured at 1.4V

Tr

Measured between 0.8V

and 2.0V, CL=30pF

Tf

Measured between 2.0V

and 0.8V, CL=30pF

Tskew

All outputs equally loaded,

CL=20pF

Tdelay

Tdsk-dsk

Tcyc-cyc

Tlock

Tjabs

Tj1-s

Measured at 1.4V

Measured at VDD/2 on the

CLKOUT pins of devices

Measured at 133MHz,

loaded outputs

Stable power supply, valid

clock presented on REF pin

At 10,000 cycles, CL=30pF

At 10,000 cycles, CL=30pF

PLL102-03

Low Skew Output Buffer

MIN.

75

40.0

45.0

TYP.

50.0

50.0

1.2

1.2

0

0

70

10

MAX.

180

60.0

55.0

1.5

1.5

250

±350

700

150

1.0

100

20

UNITS

MHz

%

%

ns

ns

ps

ps

ps

ps

ms

ps

ps

SWITCHING WAVEFORMS

Duty Cycle Timing

t1

t2

1.4V

1.4V

1.4V

Output - Output Skew

1.4V

Output

Output

1.4V

TSKEW

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 02/23/06 Page 3

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