PLL102-15 查看數據表（PDF） - PhaseLink Corporation

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PLL102-15

Low Skew Output Buffer

PhaseLink Corporation 

PLL102-15

Low Skew Output Buffer

Output-Output Skew

The skew between CLKOUT and the CLK(1-3) outputs is not dynamically adjusted by the

PLL. Since CLKOUT is one of the inputs to the PLL, zero phase difference is maintained

from REF_IN to CLKOUT. If all outputs are equally loaded, zero phase difference will

maintained from REF_IN to all outputs.

If applications requiring zero output-output skew, all the outputs must equally loaded.

If the CLK(1-3) outputs are less loaded than CLKOUT, CLK(1-3) outputs will lead it; if the

CLK(1-3) is more loaded than CLKOUT, CLK(1-3) will lag the CLKOUT.

Since the CLKOUT and the CLK(1-3) outputs are identical, they all start at the same time,

but difference loads cause them to have different rise times and different times crossing

the measurement thresholds.

REF_IN

CLKOUT

CLK(1-3)

Zero Delay

REF_IN input and all outputs loaded equally

REF_IN

CLKOUT

CLK(1-3)

Advanced

REF_IN and CLK(1-3) outputs loaded equally,

with CLK(1-3) less loaded than CLKOUT.

REF_IN

CLKOUT

CLK(1-3)

Delayed

REF_IN input and CLK(1-3) outputs loaded equally, with

CLK(1-3) more loaded than CLKOUT.

47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991

Rev 05/06/03 Page 6

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