PLL103-01XI 查看數據表（PDF） - PhaseLink Corporation

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PLL103-01XI

Low Skew Buffers

PhaseLink Corporation 

2. BYTE 1: SDRAM(8:15) Clock Register (1=Enable, 0=Disable)

Bit

Pin#

Default Description

Bit 7

45

Bit 6

44

Bit 5

41

Bit 4

40

Bit 3

36

Bit 2

35

Bit 1

32

Bit 0

31

1

SDRAM15 (Active/Inactive)

1

SDRAM14 (Active/Inactive)

1

SDRAM13 (Active/Inactive)

1

SDRAM12 (Active/Inactive)

1

SDRAM11 (Active/Inactive)

1

SDRAM10 (Active/Inactive)

1

SDRAM9 (Active/Inactive)

1

SDRAM8 (Active/Inactive)

PLL103-01

Low Skew Buffers

3. BYTE 2: SDRAM(16:17) Clock Register (1=Enable, 0=Disable)

Bit

Pin#

Default Description

Bit 7

28

Bit 6

21

Bit 5

-

Bit 4

-

Bit 3

-

Bit 2

-

Bit 1

-

Bit 0

-

1

SDRAM17 (Active/Inactive)

1

SDRAM16 (Active/Inactive)

1

Reserved

1

Reserved

1

Reserved

1

Reserved

1

Reserved

1

Reserved

47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991

Rev 03/08/00 Page 4

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