PLL103-05SI 查看數據表（PDF） - PhaseLink Corporation
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PLL103-05SI Datasheet PDF : 4 Pages
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Preliminary PLL103-05
1-to-5 Clock Distribution Buffer
PIN DESCRIPTIONS
Name
FIN
CLK1
CLK2
CLK3
CLK4
GND
VDD
CLK5
Number
1
2
3
4
5
6
7
8
Type
I
O
O
O
O
P
P
O
Description
Input Clock Frequency (FIN range 0 ~ 160MHz).
Buffered Clock Output.
Buffered Clock Output.
Buffered Clock Output.
Buffered Clock Output.
Ground.
3.3V Power Supply.
Buffered Clock Output.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 09/26/00 Page 2
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