PLL103-11SM 查看數據表（PDF） - PhaseLink Corporation

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PLL103-11SM

Low Skew Buffers

PhaseLink Corporation 

2. BYTE 1: SDRAM(6:11) Clock Register (1=Enable, 0=Disable)

Bit

Pin#

Default Description

Bit 7

27

Bit 6

26

Bit 5

23

Bit 4

22

Bit 3

-

Bit 2

-

Bit 1

19

Bit 0

18

1

SDRAM11 (Active/Inactive)

1

SDRAM10 (Active/Inactive)

1

SDRAM9 (Active/Inactive)

1

SDRAM8 (Active/Inactive)

1

Reserved

1

Reserved

1

SDRAM7 (Active/Inactive)

1

SDRAM6 (Active/Inactive)

3. BYTE 2: SDRAM12 Clock Register (1=Enable, 0=Disable)

Bit

Pin#

Default Description

Bit 7

-

Bit 6

12

Bit 5

-

Bit 4

-

Bit 3

-

Bit 2

-

Bit 1

-

Bit 0

-

1

Reserved

1

SDRAM12 (Active/Inactive)

1

Reserved

1

Reserved

1

Reserved

1

Reserved

1

Reserved

1

Reserved

PLL103-11

Low Skew Buffers

47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991

Rev 11/07/00 Page 4

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