PLL130-05SC 查看數據表（PDF） - PhaseLink Corporation

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PLL130-05SC

High Speed Translator Buffer to PECL (Enable Low)

PhaseLink Corporation 

PLL130-05

PIN DESCRIPTIONS

Name

GND

VDD

3x3mm QFN

Pin number

1,2,4,5,

9,13,14,15

7,10,11,12

REF_IN

3

PECL

6

PECL_BAR

8

OE

16

High Speed Translator Buffer to PECL (Enable Low)

Type

P

P

I

O

O

I

Description

Ground.

Power supply.

Reference input signal. The frequency of this signal will be reproduced

at the output (after translation to PECL level).

PECL True output.

PECL Complementary output.

Output enable (‘0’ for enable).

Internal pull-down (default is ‘0’).

ELECTRICAL SPECIFICATIONS

1. Absolute Maximum Ratings

PARAMETERS

SYMBOL

MIN.

MAX.

UNITS

Supply Voltage

Input Voltage, dc

Output Voltage, dc

Storage Temperature

Ambient Operating Temperature*

Junction Temperature

Lead Temperature (soldering, 10s)

ESD Protection, Human Body Model

VDD

4.6

V

VI

-0.5

VDD+0.5

V

VO

-0.5

VDD+0.5

V

TS

-65

150

°C

TA

-40

85

°C

TJ

125

°C

260

°C

2

kV

Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the

device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other

conditions above the operational limits noted in this specification is not implied.

* Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.

2. AC Specification

PARAMETERS

Input Frequency

Input signal swing

Output Frequency

Output Rise Time

Output Fall Time

CONDITIONS

REF_IN input

0.8V to 2.0V with no load

2.0V to 0.8V with no load

MIN. TYP. MAX. UNITS

0

1000 MHz

100

mV

0

1000 MHz

1.5

ns

1.5

ns

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/09/04 Page 2

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