PLS173A 查看數據表（PDF） - Philips Electronics
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PLS173A Datasheet PDF : 8 Pages
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Philips Semiconductors Programmable Logic Devices
Programmable logic array
(22 × 42 × 10)
Product specification
PLS173
AC ELECTRICAL CHARACTERISTICS
0°C ≤ Tamb ≤ +75°C, 4.75 ≤ VCC ≤ 5.25V, R1 = 470Ω, R2 = 1kΩ
TEST
LIMITS
SYMBOL
PARAMETER
FROM
TO
CONDITION
MIN
TYP MAX
UNIT
tPD
Propagation delay2
Input ±
Output ±
CL = 30pF
20
30
ns
tOE
Output enable1
Input ±
Output –
CL = 30pF
20
30
ns
tOD
Output disable1
Input ±
Output +
CL = 5pF
20
30
ns
NOTES:
1. For 3-State output; output enable times are tested with CL = 30pF to the 1.5V level, and S1 is open for high-impedance to High tests and
closed for high-impedance to Low tests. Output disable times are tested with CL = 5pF. High-to-High impedance tests are made to an output
voltage of VT = (VOH – 0.5V) with S1 open, and Low-to-High impedance tests are made to the VT = (VOL + 0.5V) level with S1 closed.
2. All propagation delays are measured and specified under worst case conditions.
VOLTAGE WAVEFORM
+3.0V
90%
0V
+3.0V
10%
5ns
tR tF
5ns
90%
0V
5ns
10%
5ns
MEASUREMENTS:
All circuit delays are measured at the +1.5V level
of inputs and outputs, unless otherwise specified.
Input Pulses
TEST LOAD CIRCUIT
C1
C2
INPUTS
NOTE:
C1 and C2 are to bypass VCC to GND.
VCC
+5V
S1
I0
BY
I11 DUT
BW
BX GND BZ
R1
R2
CL
OUTPUTS
TIMING DEFINITIONS
SYMBOL
PARAMETER
tPD
Propagation delay between
input and output.
tOD
Delay between input change
and when output is off (Hi-Z
or High).
tOE
Delay between input change
and when output reflects
specified output level.
TIMING DIAGRAM
I, B
1.5V
B
1.5V
tPD
1.5V
+3V
1.5V
0V
VOH
VT
1.5V
VOL
tOD
tOE
October 22, 1993
29
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