PLUS173-10 查看數據表（PDF） - Philips Electronics

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PLUS173-10

Programmable logic array (22 × 42 × 10)

Philips Electronics 

Philips Semiconductors Programmable Logic Devices

Programmable logic array

(22 × 42 × 10)

Product specification

PLUS173–10

LOGIC PROGRAMMING

The PLUS173–10 is fully supported by

industry standard (JEDEC compatible) PLD

CAD tools, including Philips Semiconductors

SNAP design software package. ABEL™ and

CUPL™ design software packages also

support the PLUS173–10 architecture.

All packages allow Boolean and state

equation entry formats. SNAP, ABEL and

CUPL also accept, as input, schematic

capture format.

PLUS173–10 logic designs can also be

generated using the program table entry

format, which is detailed on the following

page. This program table entry format is

supported by SNAP only.

To implement the desired logic functions, the

state of each logic variable from logic

equations (I, B, O, P, etc.) is assigned a

symbol. The symbols for TRUE,

COMPLEMENT, INACTIVE, PRESET, etc.,

are defined below.

PROGRAMMING AND

SOFTWARE SUPPORT

Refer to Section 9 (Development Software)

and Section 10 (Third-party Programmer/

Software Support) of this data handbook for

additional information.

OUTPUT POLARITY – (B)

S

B

X

ACTIVE LEVEL

HIGH1

(NON-INVERTING)

CODE

H

AND ARRAY – (I, B)

I, B

I, B

I, B

I, B

I, B

I, B

I, B

S

B

X

ACTIVE LEVEL

LOW

(INVERTING)

CODE

L

I, B

I, B

I, B

I, B

I, B

STATE

INACTIVE1, 2

P, D

CODE

O

OR ARRAY – (B)

P

S

STATE

I, B

P, D

CODE

H

P

STATE

I, B

S

P, D

CODE

L

STATE

DON’T CARE

P, D

CODE

–

VIRGIN STATE

A factory shipped virgin device contains all

fusible links intact, such that:

1. All outputs are at “H” polarity.

2. All Pn terms are disabled.

3. All Pn terms are active on all outputs.

Pn STATUS

ACTIVE1

CODE

A

Pn STATUS

INACTIVE

CODE

•

NOTES:

1. This is the initial unprogrammed state of all link pairs. It is normally associated with all unused

(inactive) AND gates Pn, Dn.

2. Any gate Pn, Dn will be unconditionally inhibited if both the true and complement of any input

(I, B) are left intact.

ABEL is a trademark of Data I/O Corp.

CUPL is a trademark of Logical Devices, Inc.

October 22, 1993

46

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