PM3386-BI 查看數據表（PDF） - PMC-Sierra

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PM3386-BI

DUAL GIGABIT ETHERNET CONTROLLER

PMC-Sierra 

RELEASED

DATASHEET

PMC-1991129

ISSUE 7

PM3386

DUAL GIGABIT ETHERNET CONTROLLER

Signal Name

TX_EN0

TX_ER0

RX_CLK0

RXD0[0]

RXD0[1]

RXD0[2]

RXD0[3]

RXD0[4]

RXD0[5]

RXD0[6]

RXD0[7]

Direction

Output

Output

Schmitt

Input

Input

Pin No.

AE23

AF24

AC21

AF20

AD19

AE20

AF21

AD20

AE21

AF22

AD21

Function

Transmit Enable (Port 0)

When in GMII mode this signal is an active

high signal asserted when valid data is

present on the TXD0[7:0] and TX_ER0

pins. This signal is updated on the rising

edge of GTX_CLK0.

When in SERDES mode this signal

enables operation of the external

transmitter. When asserted (default active

low) it indicates the potential presence of

valid transmit data. When de-asserted

indicates the absence of valid transmit

data. Note that while in SERDES mode

the polarity of this signal is programmable

to support interoperability with differing

optical transmitters.

GMII Transmit Coding Error (Port 0)

Active high signal asserted when an error

is detected during transmission. Please

refer to the Operations section for a full

listing of error conditions reported by the

PM3386 using the TX_ER0 output.

This signal is updated on the rising edge of

GTX_CLK0.

GMII Receive Clock (Port 0)

125 MHz GMII reference clock received

from the PHY device.

GMII Receive Data (Port 0)

Byte-wide receive data is input on these

pins synchronously from the PHY device.

The least significant bit, RXD0[0] is

expected to contain the first bit received on

the line.

This signal is synchronized to RX_CLK0.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

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