PM6670AS(2008) 查看數據表（PDF） - STMicroelectronics

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PM6670AS
(Rev.:2008)

Complete DDR2/3 memory power supplies controller

STMicroelectronics 

PM6670AS

Electrical characteristics

Table 6.

Electrical characteristics (continued)

TA = -25 °C to 85 °C , VCC = AVCC = +5 V and LDOIN connected to VDDQ output if not

otherwise specified (1)

Symbol

Parameter

Test condition

Min

Typ Max Unit

VDDQ Output threshold

synchronous for final tracking

to non-tracking discharge

transition

0.2

0.4

0.6

V

VTT LDO section

ILDOIN,ON

LDO input bias current in full-

on state

S3 = S5 = +5 V,

No Load on VTT

ILDOIN, LDO input bias current in

STR suspend-to-RAM state

S3 = 0 V, S5 = +5 V,

No Load on VTT

ILDOIN, LDO input bias current in

STD suspend-to-disk state

S3 = S5 = 0 V, No Load on VTT

IVTTSNS, VTTSNS bias current

BIAS

S3 = +5 V, S5 = +5 V,

VVTTSNS = VVSNS /2

IVTTSNS, VTTSNS leakage current

LEAK

S3 = 0V, S5 = +5 V,

VVTTSNS = VVSNS /2

S3 = 0V, S5 = +5 V,

IVTT,LEAK VTT leakage current

VVTT = VVSNS /2

-10

LDO linear regulator output S3 = S5= +5 V, IVTT = 0 A,

voltage (DDR2)

MODE = DDRSEL = +5 V

LDO linear regulator output

voltage (DDR3)

S3 = S5= +5 V, IVTT = 0 A,

MODE = +5 V, DDRSEL = 0 V

VVTT

S3 = S5 = MODE = + 5 V,

-20

-1 mA < IVTT < 1 mA

LDO output accuracy respect S3 = S5 = MODE = +5 V,

to VTTREF

-1 A < IVTT < 1 A

-25

S3 = S5 = MODE = +5 V,

-35

-2 A < IVTT < 2 A

VVTT < 1.10*( VVSNS /2)

2

LDO source current limit

VVTT > 1.10*( VVSNS /2)

1

IVTT,CL

VVTT > 0.90*( VVSNS /2)

-3

LDO sink current limit

VVTT < 0.90*( VVSNS /2)

-1.4

VTTREF section

1

10

10

µA

1

1

1

µA

10

0.9

V

0.75

20

25

mV

35

2.3

3

1.15 1.4

A

-2.3

-2

-1.15 -1

VTTREF output voltage

VVTTREF VTTREF output voltage

accuracy respect to VSNS/2

IVTTREF VTTREF current limit

IVTTREF = 0 A, VVSNS = 1.8 V

-15 mA < IVTTREF < 15 mA,

VVSNS = 1.8 V

VTTREF = 0 or VSNS

0.9

V

-2

2

%

±40

mA

11/54

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