VE28F008-95 查看數據表（PDF） - Intel

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VE28F008-95

8 MBIT (1 MBIT x 8) FLASH MEMORY

Intel 

VE28F008

Table 2 Bus Operations

Mode

Notes RP CE OE WE A0 VPP DQ0–7 RY BY

Read

1 2 3 VIH VIL VIL VIH

X

X

DOUT

X

Output Disable

3

VIH VIL VIH VIH

X

X High Z

X

Standby

3

VIH VIH X

X

X

X High Z

X

PowerDown

VIL

X

X

X

X

X

High Z

VOH

Intelligent Identifier (Mfr)

VIH VIL VIL VIH VIL

X

89H

VOH

Intelligent Identifier (Device)

VIH VIL VIL VIH VIH

X

A2H

VOH

Write

3 4 5 VIH VIL VIH VIL

X

X

DIN

X

NOTES

1 Refer to DC Characteristics When VPP e VPPL memory contents can be read but not written or erased

2 X can be VIL or VIH for control pins and addresses and VPPL or VPPH for VPP See DC Characteristics for VPPL and VPPH

voltages

3 RY BY is VOL when the Write State Machine is executing internal block erase or byte write algorithms It is VOH when the

WSM is not busy in Erase Suspend mode or deep powerdown mode

4 Command writes involving block erase or byte write are only successfully executed when VPP e VPPH

5 Refer to Table 3 for valid DIN during a write operation

data at the outputs Chip Enable (CE) is the device

selection control and when active enables the se-

lected memory device Output Enable (OE) is the

data input output (DQ0 – DQ7) direction control and

when active drives data from the selected memory

onto the I O bus RP and WE must also be at VIH

Figure 8 illustrates read bus cycle waveforms

off all internal circuits The VE28F008 requires time

tPHQV (see AC Characteristics-Read-Only Opera-

tions) after return from powerdown until initial mem-

ory access outputs are valid After this wakeup inter-

val normal operation is restored The Command

User Interface is reset to Read Array mode and the

upper 5 bits of the Status Register are cleared to

value 10000 upon return to normal operation

Output Disable

With OE at a logic-high level (VIH) the device out-

puts are disabled Output pins (DQ0 – DQ7) are

placed in a high-impedance state

During block erase or byte write modes RP at a log-

ic-low level (VIL) will abort either operation Memory

contents of the block being altered are no longer

valid as the data will be partially written or erased

Time tPHWL after RP goes to logic-high (VIH) is re-

quired before another command can be written

Standby

CE at a logic-high level (VIH) places the VE28F008

in standby mode Standby operation disables much

of the VE28F008’s circuitry and substantially reduc-

es device power consumption The outputs (DQ0 –

DQ7) are placed in a high-impedence state indepen-

dent of the status of OE If the VE28F008 is dese-

lected during block erase or byte write the device

will continue functioning and consuming normal ac-

tive power until the operation completes

Deep Power-Down

The VE28F008 offers a deep powerdown feature

entered when RP is at VIL During read modes RP at

a logic-low level (VIL) deselects the memory places

output drivers in a high-impedence state and turns

Intelligent Identifier Operation

The intelligent identifier operation outputs the manu-

facturer code 89H and the device code A2H for

the VE28F008 The system CPU can then automati-

cally match the device with its proper block erase

and byte write algorithms

The manufacturer and device codes are read via the

Command User Interface Following a write of 90H

to the Command User Interface a read from ad-

dress location 00000H outputs the manufacturer

code (89H) A read from address location 00001H

outputs the device code (A2H) It is not necessary to

have high voltage applied to VPP to read the intelli-

gent identifier from the Command User Interface

7

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