GS820V32T 查看數據表（PDF） - Giga Semiconductor
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GS820V32T Datasheet PDF : 15 Pages
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GSI TECHNOLOGY
GS820V32Q/T
4/5/6, 2.5V I/O, 2.0mA
64K x 32 Burst
GS820V32Q/T
80-133MHz (P/L)
66MHz Flow-Thru
Features
• Single 3.3V +5%/-5% power supply
• Separate VDDQ to allow 2.375V to 3.465V output supply level
• High frequency operation: 117MHz
• Fast access time: 4.5ns Clock to Q
• Low power: 0.5mA ISB and IDD static
• FT mode pin for either flow-thru or pipeline operation
• LBO mode pin for linear or interleave (PentiumTM and X86)
burst mode
• Byte write (BWE) and global write (GW) operation
• 3 chip enable signals for easy depth expansion
• 2 cycles enable (pipeline mode) and 1 cycle disable to allow multiple
bank without data buss contention
• Compatible to both 3.3V and 2.5V interface level
• Standard Industrial Temperature Option: -40 to +85C
• JEDEC standard 100 lead package:
Q: QFP
T: TQFP
Pentium is a trademark of Intel Corp.
Functional Description
The GS820V32 is a 64Kx32 high performance synchronous SRAM
with 2 bit burst counter. It is designed to provide L2 Cache for Pen-
tiumTM and other high performance CPU. Addresses (A0-15), data
IOs (DQ1-32), chip enables (CE1, CE2, CE3), address control inputs
(ADSP, ADSC, ADV) and write control inputs (BW1, BW2, BW3,
BW4, BWE, GW) are synchronous and are controlled by a positive
edge triggered clock (CLK).
Pin configuration
Top view
NC
DQ17
DQ18
VDDQ
VSSQ
DQ19
DQ20
DQ21
DQ22
VSSQ
VDDQ
DQ23
DQ24
FT
VDD
NC
VSS
DQ25
DQ26
VDDQ
VSSQ
DQ27
DQ28
DQ29
DQ30
VSSQ
VDDQ
DQ31
DQ32
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80 NC
2
79 DQ16
3
78 DQ15
4
77 VDDQ
5
76 VSSQ
6
75 DQ14
7
74 DQ13
8
73 DQ12
9
72 DQ11
10
71 VSSQ
11
70 VDDQ
12
69 DQ10
13
68 DQ9
14
67 VSS
15
100 pin QFP / TQFP 66 NC
16
65 VDD
17
64 ZZ
18
63 DQ8
19
62 DQ7
20
61 VDDQ
21
60 VSSQ
22
59 DQ6
23
58 DQ5
24
57 DQ4
25
56 DQ3
26
55 VSSQ
27
54 VDDQ
28
53 DQ2
29
52 DQ1
30
51 NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Output enable (OE) and power down control (ZZ) are asynchro-
nous. 2 mode control pins (LBO & FT) define 4 operation modes
of linear/interleave burst order and output flow-thru/pipeline.
Burst can be initiated with either ADSP or ADSC inputs. Subse-
quent burst address are generated internally and are controlled by
ADV. The burst sequence is either interleave order (PentiumTM
and X86) or linear order and is defined by LBO.
Output registers are provided and are controlled by FT mode pin.
With FT mode pin, Output registers can be programmed in either
pipeline mode for very high frequency operation (117MHz) or
flow-thru mode for reduced latency.
Byte write operation can be obtained through byte write enable
(BWE) input combined with 4 individual byte write signals
BW1-4. In addition, global write (GW) signal is also available to
write all bytes at once.
Low power state (standby mode) can be obtained either through
the assertion of ZZ signal or simply stop the clock (CLK). In
standby mode, memory data are still retained. Low power design
of 0.5mA standby are provided on L version.
The GS820V32 operates from a 3.3V power supply and all
inputs and outputs are LVTTL compatible. Separate output
power (VDDQ) and ground (VSSQ) pins are employed to de-
couple output noise from internal circuit and VDDQ allow user
the flexibility to employ lower output supply level like 2.5V.
GS820V32’s interface level is also compatble to 2.5V supply
level.
The GS820V32 is implemented with GSI’s high performance
CMOS technology and is available in JEDEC standard 100 lead
QFP ( Q version ) and TQFP ( T version) package.
A0-15
CLK
BWE
BW1,BW2
BW3,BW4
GW
CE1,CE2, CE3
OE
ADV
ADSP, ADSC
DQ1-32
ZZ
FT
LBO
VDD
VSS
VDDQ
VSSQ
NC
Address Inputs
Clock Input
Byte Write Enable
Byte Write. BW1 for DQ1-8; BW2 for DQ9-16;
BW3 for DQ17-24; BW4 for DQ25-32
Global Write Enable
Chip Enable
Output Enable
Burst Address advance
Address Status
Data I/O
Power down control
Flow-Thru mode
Linear Burst mode
3.3V Power Supply
Ground
Output Power Supply, 2.375V to VDD
(3.465Vmax)
Output Ground
No Connect
Rev. 9/09/97
1/15
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