H8S/2463 查看數據表（PDF） - Renesas Electronics

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H8S/2463

16-Bit Single-Chip Microcomputer

Renesas Electronics 

5.4 Interrupt Sources.................................................................................................................. 88

5.4.1 External Interrupts .................................................................................................. 88

5.4.2 Internal Interrupts ................................................................................................... 89

5.5 Interrupt Exception Handling Vector Table......................................................................... 90

5.6 Interrupt Control Modes and Interrupt Operation ................................................................ 93

5.6.1 Interrupt Control Mode 0 ........................................................................................ 95

5.6.2 Interrupt Control Mode 1 ........................................................................................ 97

5.6.3 Interrupt Exception Handling Sequence ............................................................... 100

5.6.4 Interrupt Response Times ..................................................................................... 101

5.6.5 DTC Activation by Interrupt................................................................................. 102

5.7 Usage Notes ....................................................................................................................... 104

5.7.1 Conflict between Interrupt Generation and Disabling .......................................... 104

5.7.2 Instructions that Disable Interrupts ....................................................................... 105

5.7.3 Interrupts during Execution of EEPMOV Instruction........................................... 105

5.7.4 IRQ Status Registers (ISR16, ISR) ....................................................................... 105

Section 6 Bus Controller (BSC).........................................................................107

6.1 Features.............................................................................................................................. 107

6.2 Input/Output Pins ............................................................................................................... 110

6.3 Register Descriptions ......................................................................................................... 111

6.3.1 Bus Control Register (BCR) ................................................................................. 111

6.3.2 Bus Control Register 2 (BCR2) ............................................................................ 113

6.3.3 Wait State Control Register (WSCR) ................................................................... 114

6.3.4 Wait State Control Register 2 (WSCR2) .............................................................. 116

6.3.5 System Control Register 2 (SYSCR2) .................................................................. 117

6.4 Bus Control ........................................................................................................................ 118

6.4.1 Bus Specifications................................................................................................. 118

6.4.2 Advanced Mode.................................................................................................... 125

6.4.3 I/O Select Signals.................................................................................................. 126

6.5 Bus Interface ...................................................................................................................... 127

6.5.1 Data Size and Data Alignment.............................................................................. 127

6.5.2 Valid Strobes......................................................................................................... 129

6.5.3 Valid Strobes (in Glueless Extension) .................................................................. 130

6.5.4 Basic Operation Timing in Normal Extended Mode ............................................ 131

6.5.5 Basic Operation Timing in Address-Data Multiplex Extended Mode .................. 142

6.5.6 Wait Control ......................................................................................................... 150

6.6 Burst ROM Interface.......................................................................................................... 154

6.6.1 Basic Operation Timing........................................................................................ 154

6.6.2 Wait Control ......................................................................................................... 155

6.7 Idle Cycle........................................................................................................................... 156

Rev. 2.00 Aug. 20, 2008 Page xi of xlviii

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