R8830 查看數據表（PDF） - RDC Semiconductor
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R8830 Datasheet PDF : 97 Pages
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RDC®
RISC DSP Controller
19
20
22
23-37
39, 40
A19/PIO9
A18/PIO8
A17/PIO7
A16-A2
A1 , A0
78,80,82,84,
86,
88,91,94
AD0-AD7
79,81,83,85,8
7,90
93,95
43
AO8-AO15
WB
44
HLDA
45
HOLD
46
SRDY/PIO6
48
DT/ R /PIO4
49
DEN /PIO5
96
S6/ CLKDIV2 /PIO29
R8830
Address bus. Non-multiplex memory or I/O address. The A bus
is one-half of a CLKOUTA period earlier than the AD bus.
Output/Input These pins are high-impedance during bus hold or reset.
The multiplexed address and data bus for memory or I/O
accessing. The address is present during the t1 clock phase, and
the data bus phase is in t2-t4 cycle.
The address phase of the AD bus can be disabled when the
Input/Output BHE / ADEN pin with external pull-Low resister during reset.
The AD bus is in high-impedance state during bus hold or
reset condition and this bus also be used to load system
configuration information (with pull-up or pull-Low resister)
into the RESCON(F6h) register when the reset input from low
go high.
Address Only Bus, In the multiplexed address bus, the AO15 –
Output AO8 combine with the AD7 – AD0 to form a 16 bit address
bus. These pins are floating during a bus hold or reset.
Output
Write Byte. This pin active low to indicate a write cycle on the
bus. It is floating during reset.
Bus hold acknowledge. Active high. The microcontroller will
issue a HLDA in response to a HOLD request by external bus
master at the end of T4 or Ti. When the microcontroller is in
hold status (HLDA is high), the AD15-D0, A19-A0, WR ,
Output RD , DEN , S0 - S1 , S6 , BHE , DT/ R , WHB and WLB are
floating, and the UCS , LCS , PCS6 - PCS5 , MCS3 - MCS0
and PCS3 - PCS0 will be drive high. After HOLD is detected
as being low, the microcontroller will lower HLDA.
Input
Bus hold request. Active high. This pin indicates that another
bus master is requesting the local bus.
Synchronous ready. This pin performs the microcontroller that
the address memory space or I/O device will complete a data
transfer. The SRDY pin accepts a falling edge that is
Input/Output
asynchronous
accomplished
to CLKOUTA
by elimination
and is
of the
active high. SRDY is
one-half clock period
required to internally synchronize ARDY. Tie SRDY high the
microcontroller is always assert in the ready condition. If the
SRDY is not used, tie this pin low to yield control to ARDY.
Data transmit or receive. This pin indicates the direction of
Output/Input data flow through an external data-bus transceiver. DT/ R low,
the microcontroller receives data. When DT/R is asserted high,
the microcontroller writes data to the data bus.
Data enable. This pin is provided as a data bus transceiver
Output/Input output enable. DEN is asserted during memory and I/O access.
DEN is drived high when DT/ R changes state. It is floating
during bus hold or reset condition.
Bus cycle status bit6/clock divided by 2. For S6 feature, this
pin is low to indicate a microcontroller-initiated bus cycle or
high to indicate a DMA-initiated bus cycle during T2, T3, Tw
Output/Input and T4. For CLKDIV2 feature. The internal clock of
microcontroller is the external clock be divided by 2.
(CLKOUTA, CLKOUTB=X1/2), if this pin held low during
power-on reset. The pin is sampled on the rising edge of
RDC Semiconductor Co.
Subject to change without notice
10
Rev:1.4
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