R8830 查看數據表（PDF） - RDC Semiconductor

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R8830

16-Bit RISC Microcontroller User’s Manual

RDC Semiconductor 

RDC®

RISC DSP Controller

R8830

RST .

97

UZI /PIO26

Output/Input

Upper zero indicate. This

A19-A16. It asserts in the

pin is the logical OR of the inverted

T1 and is held throughout the cycle.

Chip Select Unit Interface

Midrange memory chip selects. For MCS feature, these pins

50

MCS0 /PIO14

are active low when enable the MMCS(A6h) register to access

51

68

MCS1 /PIO15

MCS2 /PIO24

a memory. The address ranges are programmable.

Output/Input

MCS3 - MCS0 are held high during bus hold. When

69

MCS3 / RFSH /PIO25

programming LMCS(A2h) register, pin69 is as a RFSH pin to

auto refresh the PSRAM.

Upper memory chip select/ONCE mode request 1. For UCS

feature, this pin acts low when system accesses the defined

portion memory block of the upper 512K bytes (80000h-

FFFFFh) memory region. UCS default acted address region is

from F0000h to FFFFFh after power-on reset. The address

57

UCS / ONCE1

Output/Input range acting UCS is programmed by software. For ONCE1

feature. If ONCE0 and ONCE1 are sampled low on the

rising edge of RST . The microcontroller enters ONCE mode.

In ONCE mode, all pins are high-impedance. This pin

incorporates weakly pull-up resistor.

Lower memory chip select/ONCE mode request 0. For LCS

feature, this pin acts low when the microcontroller accesses the

defined portion memory block of the lower 512K (00000h-

58

LCS / ONCE0

Output/Input 7FFFFh) memory region. The address range acting LCS is

programmed by software.

For ONCE0 feature, see UCS / ONCE1 description. This pin

incorporates weakly pull-up register.

Peripheral chip selects/latched address bit. For PCS feature,

these pins act low when the microcontroller accesses the fifth

or sixth region of the peripheral memory (I/O or memory

space). The base address of PCS is programmable. These pins

59

60

PCS6 /A2/PIO2

PCS5 /A1/PIO3

Output/Input

assert

hold.

with

the

AD

address

bus

and

are

not

float

during

bus

For latched address bit feature. These pins output the latched

address A2, A1 when cleared the EX bit in the MCS and

PCS auxiliary register. The A2, A1 retains previous latched

data during bus hold.

Peripheral chip selects. These pins act low when the

62

PCS3 / RTS1/ RTR1/PIO19

microcontroller accesses the defined memory area of the

peripheral memory block (I/O or memory address). For I/O

63

65

PCS2 / CTS1/ ENRX1 PIO18

PCS1 /PIO17

Output/Input

accessed,

00000h to

the base

0FFFFh.

address

can

be

programmed

in

the

region

66

PCS0 /PIO16

For memory address access, the base address can be located in

the 1M byte memory address region. These pins assert with the

multiplexed AD address bus and are not float during bus hold.

Interrupt Control Unit Interface

Nonmaskable Interrupt. The NMI is the highest priority

hardware interrupt and is nonmaskable. When this pin is

47

NMI

Input asserted (NMI transition from low to high), the microcontroller

always transfers the address bus to the location specified by the

nonmaskable interrupt vector in the microcontroller interrupt

RDC Semiconductor Co.

Subject to change without notice

11

Rev:1.4

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