RA8870 查看數據表（PDF） - RAIO
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RA8870 Datasheet PDF : 9 Pages
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Version 1.0
5-7 KEYSCAN Interface
Pin Name
PWM1
PWM2
I/O Pin Description
O PWM signal output 1
O PWM signal output 2
RA8875
Character / Graphic TFT LCD Controller
5-8 Clock and Power Interface
Pin Name
XI
XO
RST#
TEST[2:0]
VDDP
CORE_VDD
LDO_VDD
OSC_VDDP
OSC_VDD
OSC_GNDP
OSC_GND
ADC_VDD
ADC_GND
GND
I/O Pin Description
Crystal Input Pin
I Input pin for internal crystal circuit. It should be connected to external
crystal circuit. That will generate the system clock for RA8875.
Crystal Output Pin
O Output pin for internal crystal circuit. It should be connected to external
crystal circuit. That will generate the system clock for RA8875.
Reset Signal Input
This active-low input performs a hardware reset on the RA8875. It is a
I Schmitt-trigger input with pull-up resistor for enhanced noise immunity;
however, care should be taken to ensure that it is not triggered if the
supply voltage is lowered.
I
Test Mode Input
For chip test function, should be connected to GND for normal operation.
P
IO VDD
3.3V IO power input.
P
CORE VDD
1.8 V Core power input.
LDO VDD Output
P 1.8V power generated by internal LDO. It must connect bypass capacities
to prevent power noise.
P
OSC IO VDD
The separated OSC 3.3V IO power.
OSC VDD
P OSC 1.8 V power output. It is used by OSC core. It is suggested to
connect the bypass capacitor nearby the pad.
P
OSC IO GND
The separated OSC IO ground signal.
P
OSC GND
OSC ground signal and are internally connected to OSC_GNDP.
P
ADC VDD
ADC 3.3V power signal.
P
ADC GND
ADC ground signal
P
GND
IO Cell/Core ground signal
RAiO TECHNOLOGY INC.
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