ADSP-21MOD980N-000 查看數據表（PDF） - Analog Devices

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ADSP-21MOD980N-000

MultiPort Internet Gateway Processor

Analog Devices 

PRELIMINARY TECHNICAL DATA

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ADSP-21mod980N

DATA MEMORY

ALWAYS

A C C E SS IB L E

AT ADDRESS

0x2000 - 0x3FFF

0x0000 - 0x1FFF

0x0000 - 0x1FFF

ACCESSIBLE W HEN

DM OVLAY = 0

0x0000 - 0x1FFF

ACCESSIBLE WHEN

DM OVLAY = 4

0x0000 - 0x1FFF

ACCESSIBLE W HEN

DM OVLAY = 5

0x0000 - 0x1FFF

IN TER NA L

MEMORY

ACCESSIBLE W HEN

DM OVLAY = 6

ACCESSIBLE W HEN

DM OVLAY = 7

0x0000 - 0x1FFF

ACCESSIBLE WHEN

DM OVLAY = 8

Table 5. DMOVLAY bits

DMOVLAY Memory A13

0, 4, 5, 6, 7, 8 Internal Not

Applicable

A[12:0]

Not

Applicable

MEMORY MAPPED REGISTERS (NEW TO THE

ADSP-21MOD980N)

The ADSP-21mod980N has three memory mapped regis-

ters that differ from other ADSP-21xx Family DSPs. See

“Waitstate Control Register” on page 11. See

“Programmable Flag & Composite Select Control Regis-

ter” on page 12. See “System Control Register” on

page 12. The slight modifications to these registers provide

the ADSP-21mod980N’s waitstate and BMS control

features.

DATA MEMORY

32 MEMORY

MAPPED

REGISTERS

INTERNAL

8160 WORDS

8K INTERNAL

DMOVLAY =

0, 4, 5, 6, 7, 8

ADDR

0x3FFF

0x3FE0

0x3FDF

0x2000

0x1FFF

Figure 5. Data Memory Map

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

.

11111111

11

1 1 1 1 1 1 DM (0x3FFE)

D W A IT

IOW AIT 3

IOW AIT 2

IOW AIT 1

IOW AIT 0

Wait State Mode Select

0 = Normal mode (PWAIT, DWAIT, IOWAIT0-3 = N wait states, ranging from 0 to 7)

1 = 2N+1 mode (PWAIT, DWAIT, IOWAIT0-3 = 2N+1 wait states, ranging from 0 to 15)

Figure 6. Waitstate Control Register

REV. PrB 6/2001

11

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