ADSP-21MOD980N-000 查看數據表（PDF） - Analog Devices

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ADSP-21MOD980N-000

MultiPort Internet Gateway Processor

Analog Devices 

PRELIMINARY TECHNICAL DATA

ADSP-21mod980N For current information contact Analog Devices at (800) ANALOGD

Table 1. Common Mode Pins

Pin Name(s)

# of Pins Input/Output

Function

RESET

BR

BG

IRQ2 /

8

I

8

I

8

O

8

I

Processor Reset Input

Bus Request Input

Bus Grant Output

Edge- or Level-Sensitive Interrupt Request1

PF7

IRQL1 /

PF6

IRQL0 /

PF5

IRQE /

8

I/O

8

I

8

I/O

8

I

8

I/O

8

I

Programmable I/O Pin

Level-Sensitive Interrupt Requests1

Programmable I/O Pin

Level-Sensitive Interrupt Requests1

Programmable I/O Pin

Edge-Sensitive Interrupt Requests1

PF4

8

I/O

Mode C /

1

I

Programmable I/O Pin

Mode Select Input - Checked Only During RESET

PF2

1

I/O

Mode B /

1

I

PF1

1

I/O

Mode A /

1

I

PF0

1

I/O

CLKIN

1

I

Programmable I/O Pin During Normal Operation

Mode Select Input - Checked Only During RESET

Programmable I/O Pin During Normal Operation

Mode Select Input - Checked Only During RESET

Programmable I/O Pin During Normal Operation

Clock Input

CLKOUT

8

O

SPORT

28

I/O

Processor Clock Output

Serial Port I/O Pins2

VDD and GND

175

I

Power and Ground

EZ-Port

16

I/O

For Emulation Use

1 Interrupt/Flag Pins retain both functions concurrently. If IMASK is set to enable the corresponding interrupts, then the ADSP-21mod980N will vector

to the appropriate interrupt vector address when the pin is asserted, either by external devices, or set as a programmable flag.

2 SPORT configuration determined by the ADSP-21mod980N System Control Register. Software configurable.

MEMORY INTERFACE PINS

The ADSP-21mod980N modem pool is used in Slave

Mode. In Slave Mode, the Modem Processors operate in

host configuration. The operating mode is determined by

the state of the Mode C pin during RESET and cannot be

changed while the modem pool is running. See the “Mem-

ory Architecture” section for more information.

6

6/2001 REV. PrB

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