CY7C4801 查看數據表（PDF） - Cypress Semiconductor

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CY7C4801

8K x 9 x 2 Double Sync FIFO

Cypress Semiconductor 

CY7C4801/4811/4821

CY7C4831/4841/4851

Logic Block Diagram

DA 0-8

DB0-8

WCLKA

WCLKB

WENA1

WENA2/LDA

WENB1

WENB2/LDB

INPUT

REGISTER

INPUT

REGISTER

FLAG

PROGRAM

REGISTER

FLAG

LOGIC

LDA

LDB

EFA

PAEA

PAFA

FFA

EFB

PAEB

PAFB

FFB

WRITE

CONTROL

WRITE

POINTER A

WRITE

CONTROL

WRITE

POINTER B

RAM

ARRAY A

25.6x9

.

8k x 9

RAM

ARRAY B

25.6 x 9

.

8k x 9

RSA

RSB

RESET

LOGIC

THREE–STATE

OUTPUT REGISTER

OEA

QA0-8

THREE–STATE

OUTPUT REGISTER

OEB

QB0-8

READ

POINTER A

READ

CONTROL A

RCLKA

RENA1

RENA2

READ

POINTER B

READ

CONTROL B

RCLKB

RENB1

RENB2

Pin Configuration

TQFP

Top View

48X1–1

QA1

1

QA2

2

QA3

3

QA4

4

QA5

5

QA6

6

QA7

7

QA8

8

Vcc

9

WENA2/LDA

10

WCLKA

11

WENA1

12

RSA

13

DA8

14

DA7

15

DA6

16

CY7C4801

CY7C4811

CY7C4821

CY7C4831

CY7C4841

CY7C4851

48

QB0

47

FFB

46

EFB

45

OEB

44

RENB2

43

RCLKB

42

RENB1

41

GND

40

Vcc

39

PAEB

38

PAFB

37

DB0

36

35

34

DB1

DDBB23

33

DB4

48X1–1

Document #: 38-06005 Rev. *A

Page 2 of 23

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