CY7C4801 查看數據表（PDF） - Cypress Semiconductor
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CY7C4801 Datasheet PDF : 23 Pages
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CY7C4801/4811/4821
CY7C4831/4841/4851
Pin Definitions
Signal Name Description
DA0 − 8
DB0 − 8
QA0 − 8
QB0 − 8
WENA1
WENB1
Data Inputs
Data Inputs
Data Outputs
Data Outputs
Write Enable 1
WENA2/LDA
WENB2/LDB
Dual Mode Pin
Write Enable 2
Load
RENA1
RENA2
RENB1
RENB2
WCLKA
WCKLB
Read Enable
Inputs
Write Clock
RCLKA
RCLKB
EFA,EFB
FFA,FFB
PAEA
PAEB
PAFA
PAFB
RSA
RSB
OEA
OEB
Read Clock
Empty Flag
Full Flag
Programmable
Almost Empty
Programmable
Almost Full
Reset
Output Enable
I/O
Description
I Data Inputs for 9-bit bus
I Data Inputs for 9-bit bus
O Data Outputs for 9-bit bus
O Data Outputs for 9-bit bus
I WENA1 and WENB1become the only write enables when the device is configured to
have programmable flags. Data is written on a LOW-to-HIGH transition of WCLK when
(WENA1,WENB1) is LOW and (FFA,FFB) is HIGH. If the FIFO is configured to have two write
enables, data is written on a LOW-to-HIGH transition of WCLK when (WENA1,WENB1) is
LOW and (WENA2/LDA,WENB2/LDB) and (FFA,FFB) are HIGH.
I If HIGH at reset, this pin operates as a second write enable. If LOW at reset, this pin
I
operates as a control to write or read the programmable flag offsets. (WENA1,WENB1)
must be LOW and (WENA2/LDA,WENB2/LDB) must be HIGH to write data into the FIFO.
Data will not be written into the FIFO if the (FFA,FFB) is LOW. If the FIFO is configured to have
programmable flags, (WENA2/LDA,WENB2/LDB) is held LOW to write or read the program-
mable flag offsets.
I Enables the device for Read operation.
I The rising edge clocks data into the FIFO when (WENA1,WENB1) is LOW and
(WENA2/LDA,WENB2/LDB) is HIGH and the FIFO is not Full. When
(WENA2/LDA,WENB2/LDB) is asserted, WCLK writes data into the programmable flag-offset
register.
I The rising edge clocks data out of the FIFO when (RENA1 ,RENB1) and (RENA2,RENB2)
are LOW and the FIFO is not Empty. When (WENA2/LDA,WENB2/LDB) is LOW,
(RCLKA,RCLKB) reads data out of the programmable flag-offset register.
O When (EFA,EFB) is LOW, the FIFO is empty. (EFA,EFB) is synchronized to
(RCLKA,RCLKB).
O When (FFA,FFB) is LOW, the FIFO is full. (FFA,FFB) is synchronized to (WCLKA,WCLKB).
O When (PAEA,PAEB) is LOW, the FIFO is almost empty based on the almost empty offset value
programmed into the FIFO. PAE is synchronized to RCLK.
O When (PAFA,PAFB) is LOW, the FIFO is almost full based on the almost full offset value
programmed into the FIFO. PAF is synchronized to WCLK.
I Resets device to empty condition. A reset is required before an initial read or write
operation after power-up.
I When (OEA,OEB) is LOW, the FIFO’s data outputs drive the bus to which they are connected.
If (OEA,OEB) is HIGH, the FIFO’s outputs are in High Z (high-impedance) state.
Document #: 38-06005 Rev. *A
Page 4 of 23
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