CY7C4801 查看數據表（PDF） - Cypress Semiconductor

零件编号

产品描述 (功能)

生产厂家

CY7C4801

8K x 9 x 2 Double Sync FIFO

Cypress Semiconductor 

CY7C4801/4811/4821

CY7C4831/4841/4851

Switching Waveforms (continued)

Reset Timing[13]

tRS

RSA(RSB)

RENA1, RENA2

(RENB1,RENB2)

tRSS

tRSS

tRSR

tRSR

WENA1

(WENB1)

tRSS

tRSR

WENA2/LDA

[15]

(WENB2/LDB)

tRSF

EFA, PAEA

(EFB, PAEB)

tRSF

FFA, PAFA

(FFB, PAFB)

QA0−QA8

(QB0−QB8)

tRSF

[14]

OEA(OEB)=1

OEA(OEB)=0

48X1–8

Notes:

13. The clocks (RCLKA,RCLKB, WCLKA,WCLKB) can be free-running during reset.

14. After reset, the outputs will be LOW if (OEA,OEB) = 0 and three-state if (OEA,OEB)=1.

15. Holding (WENA2/LDA,WENB2/LDB) HIGH during reset will make the pin act as a second enable pin. Holding(WENA2/LDA,WENB2/LDB) LOW during reset will make

the pin act as a load enable for the programmable flag offset registers.

Document #: 38-06005 Rev. *A

Page 8 of 23

Share Link: