CY7C4801 查看數據表（PDF） - Cypress Semiconductor

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CY7C4801

8K x 9 x 2 Double Sync FIFO

Cypress Semiconductor 

CY7C4801/4811/4821

CY7C4831/4841/4851

Switching Waveforms (continued)

First Data Word Latency after Reset with Simultaneous Read and Write

WCLKA,WCLKB

DA0−DA8

(DB0−DB8)

tDS

tENS

WENA1(WENB1)

WENA2(WENB2)

(if applicable)

RCLKA(RCLKB)

EFA(EFB)

D0 (FIRSTVALID WRITE)

[16]

tFRL

tSKEW1

D1

tREF

D2

[17]

tA

D3

D4

tA

RENA1, RENA2

(RENB1,RENB2)

QA0 −QA8

(QB0−QB8)

OEA(OEB)

tOLZ

tOE

D0

D1

48X1–9

Notes:

16. When tSKEW1 > minimum specification, tFRL (maximum) = tCLK + tSKEW1. When tSKEW1 < minimum specification, tFRL (maximum) = either 2*tCLK + tSKEW1 or tCLK + tSKEW1.

The Latency Timing applies only at the Empty Boundary (EFA, EFB= LOW).

17. The first word is available the cycle after (EFA, EFB) goes HIGH, always.

Document #: 38-06005 Rev. *A

Page 9 of 23

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