RT8056 查看數據表（PDF） - Richtek Technology
零件编号
产品描述 (功能)
生产厂家
RT8056 Datasheet PDF : 11 Pages
| |||
RT8056
polymer, aluminum electrolytic and ceramic capacitors are
all available in surface mount packages. Special polymer
capacitors offer very low ESR, but have lower capacitance
density than other types. Tantalum capacitors have the
highest capacitance density, but it is important to only use
types that have been surge tested for use in switching
power supplies. Aluminum electrolytic capacitors have
significantly higher ESR, but can be used in cost-sensitive
applications, provided that consideration is given to ripple
current ratings and long-term reliability. Ceramic capacitors
have excellent low ESR characteristics, but can have a
high voltage coefficient and audible piezoelectric effects.
The high Q of ceramic capacitors with trace inductance
can also lead to significant ringing.
Using Ceramic Input and Output Capacitors
Higher value, lower cost ceramic capacitors are now
becoming available in smaller case sizes. Their high ripple
current, high voltage rating and low ESR make them ideal
for switching regulator applications. However, care must
be taken when these capacitors are used at the input and
output. When a ceramic capacitor is used at the input and
the power is supplied by a wall adapter through long wires,
a load step at the output can induce ringing at the input,
VIN. At best, this ringing can couple to the output and be
mistaken as loop instability. At worst, a sudden inrush of
current through the long wires can potentially cause a
voltage spike at VIN large enough to damage the part.
Output Voltage Programming
The resistive divider allows the FB pin to sense a fraction
of the output voltage as shown in Figure 1.
VOUT
R1
FB
RT8056
R2
GND
Figure 1. Setting the Output Voltage
For adjustable voltage mode, the output voltage is set by
an external resistive divider according to the following
equation :
VOUT = VREF x (1+ R1/R2)
where VREF is the internal reference voltage (0.6V typical)
DS8056-02 April 2011
Thermal Considerations
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature. The
maximum power dissipation can be calculated by the
following formula :
PD(MAX) = (TJ(MAX) − TA) / θJA
Where TJ(MAX) is the maximum junction temperature, TA
is the ambient temperature, and θJA is the junction to
ambient thermal resistance.
For recommended operating condition specifications of
RT8056, the maximum junction temperature is 125°C and
TA is the ambient temperature. The junction to ambient
thermal resistance, θJA, is layout dependent. For
WDFN-10L 3x3 packages, the thermal resistance, θJA, is
70°C/W on a standard JEDEC 51-7 four-layer thermal test
board. The maximum power dissipation at TA = 25°C can
be calculated by the following formula :
PD(MAX) = (125°C − 25°C) / (70°C/W) = 1.429W for
WDFN-10L 3x3 package
The maximum power dissipation depends on the operating
ambient temperature for fixed TJ(MAX) and thermal
resistance, θJA. For RT8056 package, the derating curve
in Figure 2 allows the designer to see the effect of rising
ambient temperature on the maximum power dissipation.
1.60
Four-Layer PCB
1.40
1.20
1.00
0.80
0.60
0.40
0.20
0.00
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 2. Derating Curve for RT8056 Package
www.richtek.com
9
Share Link: 