RT8057A 查看數據表（PDF） - Richtek Technology
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RT8057A Datasheet PDF : 12 Pages
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RT8057A
For recommended operating condition specifications of
the RT8057A, the maximum junction temperature is 125°C
and TA is the ambient temperature. The junction to ambient
thermal resistance, θJA, is layout dependent. For WDFN-
6SL 2x2 package, the thermal resistance, θJA, is 120°C/
W on a standard JEDEC 51-7 four-layer thermal test board.
For TSOT-23-5 package, the thermal resistance, θJA, is
160°C/W on a standard JEDEC 51-7 four-layer thermal
test board. The maximum power dissipation at TA = 25°C
can be calculated by the following formula :
PD(MAX) = (125°C − 25°C) / (120°C/W) = 0.833W for
WDFN-6SL 2x2 package
PD(MAX) = (125°C − 25°C) / (160°C/W) = 0.625W for
TSOT-23-5 package
he maximum power dissipation depends on the operating
ambient temperature for fixed TJ(MAX) and thermal
resistance, θJA. For the RT8057A packages, the derating
curve in Figure 1 allows the designer to see the effect of
rising ambient temperature on the maximum power
dissipation.
0.9
Four-Layer PCB
0.8
0.7
0.6
WDFN-6SL 2x2
0.5
TSOT-23-5
0.4
0.3
0.2
0.1
0.0
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 2. Derating Curve for the RT8057A Package
Layout Considerations
Follow the PCB layout guidelines for optimal performance
of the RT8057A.
` Connect the terminal of the input capacitor(s), CIN, as
close as possible to the VIN pin. This capacitor provides
the AC current into the internal power MOSFETs.
` LX node experiences high frequency voltage swing and
should be kept within a small area. Keep all sensitive
small-signal nodes away from the LX node to prevent
stray capacitive noise pick up.
` Flood all unused areas on all layers with copper. Flooding
with copper will reduce the temperature rise of power
components. Connect the copper areas to any DC net
(VIN, VOUT, GND, or any other DC rail in the system).
` Connect the FB pin directly to the feedback resistors.
The resistive voltage divider must be connected between
VOUT and GND.
LX should be connected to inductor by
wide and short trace. Keep sensitive
components away from this trace.
COUT
VOUT
L1
LX 1
VOUT
NC 2
C1 FB 3
R1
R2
6 GND
5 VIN
CIN
7 4 EN
Input capacitor must
be placed as close to
the IC as possible.
(a) For WDFN-6SL 2x2 Package
Input capacitor must
be placed as close to
the IC as possible.
VIN 1
CIN
GND 2
EN 3
LX should be connected to
inductor by wide and short trace.
Keep sensitive components
away from this trace.
5 LX
L1 VOUT
R1
4 FB
R2
COUT
GND
(a) For TSOT-23-5 Package
Figure 3. PCB Layout Guide
www.richtek.com
10
DS8057A-00 March 2011
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