RT8100 查看數據表（PDF） - Richtek Technology

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RT8100

Synchronous buck PWM DC/DC with Dual Voltage Control Mode

Richtek Technology 

RT8100

Preliminary

Power on reset

The POR circuitry monitors the supply voltage of the chip.

When the chip power supply exceeds 4.2V, the chip

releases the reset state and works according to the

settings. Once the supply voltage is lower than 4.0V, POR

circuitry resets the chip.

VIN detection

The VIN detection circuitry monitors the switching power

source when power up. As VIN > 1.8V, RR pin is enabled

for ramp setting and the chip is in ramp setting mode. The

voltage at RR pin will be about 0.5V. Otherwise, the chip

will be in VIN detection mode and RR pin is disabled for

ramp setting until VIN > 1.8V. In VIN detection mode, the

UGATE and LGATE will be off and SS will be pulled low by

a constant current of 10uA. The chip will enter the ramp

setting mode and SS will re-softstart when VIN > 1.8V.

Enable

After POR reset, the chip monitors the voltage of PI pin.

When PI is higher than 0.3V, the chip is enabled. The chip

is disabled when VPI is lower than 0.3V. With a precise

threshold voltage, the PI pin can be used for power

sequence.

Soft-start

A constant current of 10uA starts to charge the capacitor

connected to SS pin right after the chip has been powered

up and enabled. The ramp voltage on SS pin is also used

to clamp the comp voltage during soft-start, which

automatically constraints the output current due to the

nature of current mode topology. This brings up smaller

inrush current and smooth output voltage ramp. The SS

pins are also used as the timer during OCP hiccup.

Frequency setting

The converter switching frequency is programmed by

connecting a resistor from the RT pin to GND. The

frequency vs. RRT plot is shown in “Typical Operating

Characteristics”.

Output voltage setting and control

Control loops consist of an error amplifier, a pulse width

modulator, current feed back components, a gate driver

and power components. The internal high accuracy bias

provides the reference voltage of 0.8V at the non-inverting

input of both error amplifiers. The output voltage is

programmed by using a voltage divider at output and feeding

the voltage division back to corresponding error amplifiers.

As conventional current mode PWM controller, the output

voltage is locked at the VREF of error amplifier and the error

signal is used as the control signal of pulse width

modulator. The PWM signals are generated by comparison

of EA output and current ramp waves. Power stage

transforms VIN to output by PWM signal on-time ratio.

www.richtek.com

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DS8100-03 August 2007

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