RT8289 查看數據表（PDF） - Richtek Technology
零件编号
产品描述 (功能)
生产厂家
RT8289 Datasheet PDF : 13 Pages
| |||
RT8289
recovery time, VOUT can be monitored for overshoot or
ringing that would indicate a stability problem.
EMI Consideration
Since parasitic inductance and capacitance effects in PCB
circuitry would cause a spike voltage on SW pin when
high side MOSFET is turned-on/off, this spike voltage on
SW may impact on EMI performance in the system. In
order to enhance EMI performance, there are two methods
to suppress the spike voltage. One is to place an R-C
snubber between SW and GND and make them as close
as possible to the SW pin (see Figure 3). Another method
is to add a resistor in series with the bootstrap
capacitor, CBOOT. But this method will decrease the driving
capability to the high side MOSFET. It is strongly
recommended to reserve the R-C snubber during PCB
layout for EMI improvement. Moreover, reducing the SW
trace area and keeping the main power in a small loop will
be helpful on EMI performance. For detailed PCB layout
guide, please refer to the section of Layout Consideration.
VIN
5.5V to 32V
REN*
CEN*
7 VIN
BOOT 1
CIN
4.7µF x 2
RT8289
SW 8
5 EN
6, Exposed Pad (9)
GND
FB 4
RBOOT*
RS*
CS*
CBOOT L
10nF 10µH
D
B550C
* : Optional
VOUT
5V/5A
R1
10k
R2
3.16k
COUT
47µFx2
(POSCAP)
Figure 3. Reference Circuit with Snubber and Enable Timing Control
Thermal Considerations
For continuous operation, do not exceed the maximum
operation junction temperature. The maximum power
dissipation depends on the thermal resistance of IC
package, PCB layout, the rate of surroundings airflow and
temperature difference between junction to ambient. The
maximum power dissipation can be calculated by following
formula :
PD(MAX) = (TJ(MAX) − TA ) / θJA
Where TJ(MAX) is the maximum operation junction
temperature , TA is the ambient temperature and the θJA is
the junction to ambient thermal resistance.
For recommended operating conditions specification of
RT8289, the maximum junction temperature is 125°C. The
junction to ambient thermal resistance θJA is layout
dependent. For PSOP-8 package, the thermal resistance
θJA is 75°C/W on the standard JEDEC 51-7 four-layers
thermal test board. The maximum power dissipation at
TA = 25°C can be calculated by following formula:
PD(MAX) = (125°C − 25°C) / (75°C/W) = 1.333W
(min.copper area PCB layout)
PD(MAX) = (125°C − 25°C) / (49°C/W) = 2.04W (70mm2
copper area PCB layout)
The thermal resistance θJA of SOP-8 (Exposed Pad) is
determined by the package architecture design and the
PCB layout design. However, the package architecture
design had been designed. If possible, it's useful to
increase thermal performance by the PCB layout copper
design. The thermal resistance θJA can be decreased by
adding copper area under the exposed pad of SOP-8
(Exposed Pad) package.
As shown in Figure 4, the amount of copper area to which
the SOP-8 (Exposed Pad) is mounted affects thermal
performance. When mounted to the standard
SOP-8 (Exposed Pad) pad (Figure 4a), θJA is 75°C/W.
Adding copper area of pad under the SOP-8 (Exposed
Pad) (Figure 4.b) reduces the θJA to 64°C/W. Even further,
increasing the copper area of pad to 70mm2 (Figure 4.e)
reduces the θJA to 49°C/W.
www.richtek.com
10
DS8289-01 March 2011
Share Link: 