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RT9594A 查看數據表(PDF) - Richtek Technology

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RT9594A Datasheet PDF : 10 Pages
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VBAT < 2.5V
VBAT
(1V/Div)
IIN
(200mA/Div)
VOUT
(50V/Div)
Change to lower current
Time (1s/Div)
Figure 7. Lower Charging Current
Layout Guide
For best performance, careful PCB layout is necessary.
The following guidelines should be strictly followed when
designing a PCB layout for the RT9594A/B.
1. Both of primary and secondary power paths should be
as short as possible.
2. Place the RCS as close to chip as possible. The GND
side of RCS should be directly connected to ground
plane to avoid noise coupling.
3. Keep FB node area small and far away from nodes
with voltage switching to reduce parasitic capacitance
coupling effect.
4. The PGND should be connected to VBAT ground plane
to reduce switching noise.
VBAT
VOUT
PGND
PGND
AGND
16 15 14 13
Bottom
VBAT 1
12 VDD
CS 2
VDOUT 3
FBVD 4
PGND
17
11 FB
10 STAT
9 AGND
5678
Figure 8. Suggestion Layout
DS9594A/B-02 April 2011
RT9594A/B
www.richtek.com
9

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