S-8261AAJMD-G2JT2G 查看數據表（PDF） - Seiko Instruments Inc
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S-8261AAJMD-G2JT2G Datasheet PDF : 33 Pages
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BATTERY PROTECTION IC FOR 1-CELL PACK
S-8261 Series
Rev.5.3_00
Pin Configuration
SOT-23-6
Top view
65 4
1 23
Figure 2
Pin No.
1
2
3
4
5
6
Symbol
DO
VM
CO
DP
VDD
VSS
Table 4
Description
FET gate control pin for discharge
(CMOS output)
Voltage detection pin between VM and VSS
(Overcurrent detection pin)
FET gate control pin for charge
(CMOS output)
Test pin for delay time measurement
Positive power input pin
Negative power input pin
6
Seiko Instruments Inc.
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