S3C72F5 查看數據表（PDF） - Samsung
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S3C72F5 Datasheet PDF : 41 Pages
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PRODUCT OVERVIEW
FEATURES SUMMARY
Memory
• 544 × 4-bit RAM (excluding LCD display RAM)
• 16,384 × 8-bit ROM
39 I/O Pins
• I/O: 35 pins
• Input only: 4 pins
LCD Controller/Driver
• 56 segments and 16 common terminals
• 8 and 16 common selectable
• Internal resistor circuit for LCD bias
• All dot can be switched on/off
8-bit Basic Timer
• 4 interval timer functions
• Watch-dog timer
8-bit Timer/Counter
• Programmable 8-bit timer
• External event counter
• Arbitrary clock frequency output
• External clock signal divider
• Serial I/O interface clock generator
16-Bit Timer/Counter
• Programmable 16-bit timer
• External event counter
• Arbitrary clock frequency output
• External clock signal divider
8-bit Serial I/O Interface
• 8-bit transmit/receive mode
• 8-bit receive mode
• LSB-first or MSB-first transmission selectable
• Internal or external clock source
Memory-Mapped I/O Structure
• Data memory bank 15
S3C72F5/P72F5
Watch Timer
• Time interval generation: 0.5 s, 3.9 ms
at 32768 Hz
• 4 frequency outputs to BUZ pin
• Clock source generation for LCD
Interrupts
• Four internal vectored interrupts
• Four external vectored interrupts
• Two quasi-interrupts
Bit Sequential Carrier
• Supports 16-bit serial data transfer in arbitrary
format
Power-Down Modes
• Idle mode (only CPU clock stops)
• Stop mode (main system oscillation stops)
• Subsystem clock stop mode
Oscillation Sources
• Crystal, ceramic, or RC for main system clock
• Crystal oscillator for subsystem clock
• Main system clock frequency: 0.4 – 6 MHz
• Subsystem clock frequency: 32.768 kHz
• CPU clock divider circuit (by 4, 8, or 64)
Instruction Execution Times
• 0.67, 1.33, 10.7 µs at 6 MHz
• 0.95, 1.91, 15.3 µs at 4.19 MHz
• 122 µs at 32.768 kHz
Operating Temperature
• – 40 °C to 85 °C
Operating Voltage Range
• 1.8 V to 5.5 V
Package Type
• 100-pin QFP
1–2
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