S3C72F5 查看數據表（PDF） - Samsung

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S3C72F5

The S3C72F5 single-chip CMOS microcontroller has been designed for high performance using Samsung's newest 4-bit CPU core, SAM47

Samsung 

S3C72F5/P72F5

BLOCK DIAGRAM

PRODUCT OVERVIEW

P1.0-P1.3/

INT0-INT4

P2.0/CLO

P2.1/LCDCK

P2.2/LCDSY

P3.0/TCLO0

P3.1/TCLO1

P3.2/TCL0

P3.3/TCL1

P4.0–P4.3/

COM8-COM11

P5.0–P5.3/

COM12-COM15

P6.0–P6.3/

SEG55-SEG52/

KS4–KS7

P7.0–P7.3/

SEG51-SEG48

INPUT PORT 1

I/O PORT 2

I/O PORT 3

I/O PORT 4

I/O PORT 5

I/O PORT 6

I/O PORT 7

P8.0–P8.3/

SEG47-SEG44

P9.0–P9.3/

SEG43-SEG40

I/O PORT 8

I/O PORT 9

RESET

Xin Xout

XTin XTout

BASIC

TIMER

WATCH

TIMER

INTERRUPT

CONTROL

BLOCK

CLOCK

INTERNAL

INTERRUPTS

INSTRUCTION

DECODER

ARITHMETIC

AND

LOGIC UNIT

544 x 4-BIT

DATA

MEMORY

INSTRUCTION

REGISTER

PROGRAM

COUNTER

LCD

DRIVER/

CONTROLLER

PROGRAM

STATUS

WORD

STACK

POINTER

16 KBYTE

PROGRAM

MEMORY

SERIAL I/O

I/O

PORT 0

8-BIT

TIMER/

COUNTER

16-BIT

TIMER/

COUNTER

VLC1-VLC5

COM0-COM7

P4.0-P5.3/

COM8-COM15

SEG0-SEG39

P9.3-P6.0/

SEG40-SEG55

P0.0/SCK/K0

P0.1/SO/K1

P0.2/SI/K2

P0.3/BUZ/K3

Figure 1-1. S3C72F5 Simplified Block Diagram

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