S3C72N8 查看數據表（PDF） - Samsung

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S3C72N8

The S3C72N2/C72N4 single-chip CMOS microcontroller has been designed for high performance using Samsungs newest 4-bit CPU core/ SAM47 (Samsung Arrange

Samsung 

S3C72N8/P72N8/C72N5/P72N5

BLOCK DIAGRAM

PRODUCT OVERVIEW

INT0, INT1, INT2

P1.3/TCL0

P2.0/TCLO0

8-Bit Timer/

Counter 0

P4.0-P4.3

P5.0-P5.3

I/O Port 4

I/O Port 5

P6.0-P6.3/

KS0-KS3

P7.0-P7.3/

KS4-KS7

I/O Port 6

I/O Port 7

P8.0-P8.7/

SEG24-SEG31

I/O Port 8

Watchdog

Timer

Basic

Timer

Watch

Timer

P2.3/BUZ

XIN XOUT

RESET XTIN XTOUT

Interrupt

Control

Block

Clock

Internal

Interrupts

Instruction Decoder

Arithmetic

and

Logic Unit

Instruction

Register

4-Bit

Accumulator

Program

Counter

Program

Status Word

Flags

Stack

Pointer

512 x 4-Bit

Data

Memory

8/16-Kbyte

Program

Memory

LCD Driver/

Controller

I/O Port 0

I/O Port 1

I/O Port 2

I/O Port 3

Serial I/O

Port

Bias

VLC0-VLC2

LCDCK/P3.0

LCDSY/P3.1

COM0-COM3

SEG0-SEG23

P8.0-P8.7/

SEG24-SEG31

P0.0/INT4

P0.1/SCK

P0.2/SO

P0.3/SI

P1.0/INT0

P1.1/INT1

P1.2/INT2

P1.3/TCL0

P2.0/TCLO0

P2.1

P2.2/CLO

P2.3/BUZ

P3.0/LCDCK

P3.1/LCDSY

P3.2

P3.3

P0.1 P0.2 P0.3

/SCK /SO /SI

Figure 1-1. S3C72N8/C72N5 Simplified Block Diagram

1-3

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