SAA2502 查看數據表（PDF） - Philips Electronics

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SAA2502

ISO/MPEG Audio Source Decoder

Philips Electronics 

Philips Semiconductors

ISO/MPEG Audio Source Decoder

Preliminary specification

SAA2502

7 FUNCTIONAL DESCRIPTION

7.1 Basic functionality

From a functional point of view, several blocks can be

distinguished in the SAA2502. A clock generator section

derives the internally and externally required clock signals

from its clock inputs. The input interface section receives

or requests coded input data in one of the supported input

interface modes. The demultiplexer processor handles

frame synchronization, parsing, demultiplexing and error

concealment of the input data stream The de-quantization

and scaling processor performs the transformation and

scaling operations on the (demultiplexed) coded sample

representations in the input bitstream to yield sub-band

domain samples.

The sub-band samples are transferred to the synthesis

sub-band filter bank processor which reconstructs the

baseband audio samples. The output interface block

transforms the audio samples to the output formats

required by the different output ports.

The decoding control block houses the I2C-bus/L3

microcontroller interface, and handles the response to

external control signals. This section enables the

application to configure the SAA2502, to read its decoding

status, to read ancillary data and so on.

Several pins are reserved for boundary scan test (5 pins)

and factory test scan chain control (2 pins).

7.2 Clock generator module

The SAA2502 clock interfacing is designed for application

versatility. It consists of 9 signals (see Table 1).

The clock generator provides the following clock signals:

• Internal sample clocks

• External buffered sample clock FSCLK

• Processor master clock

• Coded input data bit clock

• Coded input data request clock f = i--n----p----u----t-3---b2---i-t----r--a---t--e-

The module can be configured to operate in 3 different

modes of operation:

• External sample clock mode

• Free running internal sample clock mode

• Locked internal sample clock mode.

Clock generator operation mode must be stationary while

the device is in normal operation. Changing mode should

always be followed by a (soft) reset.

Table 1 Clock interfacing signals

SIGNAL

MCLKIN

MCLKOUT

MCLK24

X22IN

X22OUT

FSCLKIN

FSCLK

REFCLK

PHDIF

DIRECTION

input

output

input

input

output

input

output

input

output

FUNCTION

master clock oscillator input or signal input

master clock oscillator output

master clock frequency indication

22.5792 MHz clock oscillator input or signal input

22.5792 MHz clock oscillator output

external sample rate clock signal input

sample rate clock signal output

coded input data rate reference clock

phase difference indication output between reference clock and sample clock

1997 Nov 17

7

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