SAA2502 查看數據表（PDF） - Philips Electronics

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SAA2502

ISO/MPEG Audio Source Decoder

Philips Electronics 

Philips Semiconductors

ISO/MPEG Audio Source Decoder

Preliminary specification

SAA2502

7.2.1 EXTERNAL SAMPLE CLOCK

In applications where a 256 × fs sample clock is available,

the use of external crystals may be avoided by putting the

SAA2502 clock generator module in ‘external sample

clock mode’. Such mode setting may be realized by setting

control flag FSCINP of the control interface. In this event

the sample clock has to be provided to the FSCLKIN clock

input. If sample rate switching should be supported,

required clock frequency changes are the responsibility of

the application. After such a clock frequency change,

enforcement of a soft reset is advised.

In external sample clock mode (and only in that mode) the

clock generator module is able to accept a 384 × fs sample

clock input. If that mode of operation is desired the control

flag FSC384 should be set.

The FSCLK output is normally disabled in this mode.

If enabled (by setting control flag FSCENA) FSCLK will

produce a buffered copy of FSCLKIN.

X22IN, X22OUT, REFCLK and PHDIF are not used in this

mode. X22IN and REFCLK should be connected to GND

or VDD.

MCLKIN is used to provide the (free running) master clock.

This may either be achieved by applying a correct clock

signal to MCLKIN or by connecting a crystal between

MCLKIN and MCLKOUT. In external sample clock mode

(and only in that mode) the master clock may deviate from

24.576 MHz. The master clock frequency value required

depends on the state of pin MCLK24 (see Table 2).

Table 2 Master clock frequency setting by MCLK24

MCLK24

GND

VDD

FREQUENCY

MINIMUM

256 × fs

512 × fs

MAXIMUM

12.288 MHz

(256 × 48 kHz)

24.576 MHz

(512 × 48 kHz)

7.2.2 FREE RUNNING INTERNAL SAMPLE CLOCK

This is the default mode of operation: 256 × fs for all six

supported sample rates is generated internally from the

clock frequencies supplied to MCLKIN (24.576 MHz) and

X22IN (22.5792 MHz) as shown in Table 3.

Table 3 Internal sample clock (default mode)

SAMPLE

FREQUENCY

256 × 48 kHz

256 × 44.1 kHz

256 × 32 kHz

256 × 24 kHz

256 × 22.05 kHz

256 × 16 kHz

RESULTANT FREQUENCIES

(MHz)

12.288

2----4---.-2-5---7----6-

11.2896

2----2---.--5-2--7----9---2--

8.192

2----4---.-3-5---7----6- (1)

6.144

2----4---.-4-5---7----6-

5.6448

2----2---.--5-4--7----9---2--

4.096

2----4---.-6-5---7----6-

Note

1. Asymmetrical FSCLK.

The main advantage of this mode is that the SAA2502

determines automatically which sampling rate is active

from the sampling rate setting of the input data bit stream,

and then selects either MCLKIN or X22IN divided by the

correct number as the sample clock source.

Therefore this mode is particularly suited in applications

supporting dynamically varying sampling rates.

The required clocks may either be applied to MCLKIN

(respectively to X22IN) or be generated by connecting a

crystal between MCLKIN and MCLKOUT (respectively

between X22IN and X22OUT).

The recommended crystal oscillator configuration is

shown in Fig.3. The specified component values only

apply to crystals with a low equivalent series resistance

of <40 Ω.

FSCLKIN, REFCLK and PHDIF are not used in this mode

(FSCLKIN and REFCLK should be connected to VSS or

VDD). MCLK24 has to be connected to VDD, while the

control flags FSCINP and FSC384 should be left in their

default (cleared) states. If the FSCLK output is enabled (by

setting control flag FSCENA) FSCLK will produce a

buffered version of 256 × fs.

1997 Nov 17

8

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