SAA2502 查看數據表（PDF） - Philips Electronics

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SAA2502

ISO/MPEG Audio Source Decoder

Philips Electronics 

Philips Semiconductors

ISO/MPEG Audio Source Decoder

Preliminary specification

SAA2502

handbook, halfpaCg2e

C1

C3

C4

X1

R1

R2

X2

R4

R3

26

27

SAA2502

32

31

C1 = C2 = C3 = C4 = 10 pF;

R1 = R4 = 100 kΩ;

R2 = R3 = 1 kΩ;

X1 = 22.5792 MHz;

X2 = 24.5760 MHz.

MGE470

Fig.3 Crystal oscillator components.

7.2.3 LOCKED INTERNAL SAMPLE CLOCK

This mode differs from the previous one in just a single

aspect: the REFCLK and PHDIF pins are used to realize a

Phase-Locked Loop (PLL) which locks the 256 × fs sample

clock to the REFCLK reference clock. Because the real

goal is locking sample clock and bit rate, a reference clock

should be used which has a fixed relation to the input bit

rate. An example of such a PLL realization is shown in

Fig.4.

The phase comparator output PHDIF generates a signal

with a DC component proportional to the phase difference

between the internal signals SIG and REF (see Fig.5).

The 22.5792 MHz signal X22IN is divided by 147 and the

24.576 MHz signal MCLKIN is divided by 160. This results

in the same frequency (153.6 kHz) in both events.

One of the two signals is selected as input for the

programmable divide by N1 unit. The selector is controlled

in such a way that SIG and 256 × fs will stem from the

same source. The divisor N1 is programmable with

(1 to 16) × 8 as possible values.

REF on the other hand is derived from the REFCLK input.

Two programmable dividers in series are used here. N2

may adopt one of 4 possible values: 5, 25, 125 or 625

while N3 can be programmed to be 1 to 32. Because both

inputs of the phase comparator have to operate at identical

frequencies the next equation has to be obeyed:

R---N--E---2--F--×--C---N--L--3--K-- = 1----5---6----.N-6---1---k---H----z- or, written differently:

REFCLK = 1----5---3----.-6------k---H---N-z----1-×----N-----2----×-----N----3-

For a list of supported REFCLK frequency values

see Chapter 8.

The mode of operation of the phase comparator in Fig.5 is

programmable via the control flag PHSMOD:

handbook, halfpage

LOW-

PASS

FILTER

24.576 MHz

VCXO

22.5792 MHZ

VCXO

PHDIF MCLKIN MCLKOUT X22IN X22OUT

SAA2502

MGE471

Fig.4 External PLL components.

handbook, full pagewidth

X22IN

MCLKIN

REFCLK

DIVIDE BY

147

DIVIDE BY

160

DIVIDE BY

N2

153.6 kHz

DIVIDE BY SIG

N1

DIVIDE BY

N3

REF

PHASE

COMPA-

RATOR

MGE472

Fig.5 SAA2502 phase comparator.

PHDIF

1997 Nov 17

9

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